Can anyone please tell me that how does a 4T SRAM works (4 MOS transistors+ 2 poly resistor)? How does the internal node pulls to a high value? Is it still static or dynamic?
Electrical – 4T SRAM read and write operation
digital-logicsram
Related Solutions
Presumably the FPGA has some purpose for its SRAM connection, though you haven't specified what that is. I would guess that your best bet would be to have a means by which the Cortex can sufficiently influence how the FPGA writes to SRAM, and find out enough about what it's reading, to determine whether the SRAM is working properly. For example, if the FPGA would normally write the SRAM with data captured received from an ADC, and output it, after a delay, to a DAC, one could have a test mode that would instead write data from a linear-feedback-shift register, and another test mode that would mix data read from the SRAM into a linear-feedback-shift register with slightly different taps. If one can arrange to have each test mode run through the SRAM a controlled number of times, initializing the LFSR before the first pass and reading it after each pass, one can arrange things so that it would be unlikely a broken SRAM would yield the correct LFSR values, but the hardware could be simpler than allowing the CPU direct access, and (more importantly) the access timings would be like those the SRAM would see in actual use.
You have to keep transistors and gates apart.
Four transistors is not bad to store a bit of data. If you would use a couple of gates you'd need at least 8. (A 2-input NAND gate consists of 4 transistors.) An SRAM cell is basically two inverters connected back to back, so that they one keeps the level of the other alive. One inverter consists of 2 transistors, so that's 4 in total.
Actually it's possible to use even less hardware to store a bit, and that's what DRAM does: it stores a bit as a voltage level in a capacitor. This means that you can get a lot more data in a square mm of DRAM than in an SRAM. Unfortunately the capacitor voltage leaks away, so the DRAM has to be refreshed continuously.
Best Answer
DRAM
The DRAM works much like a 1T or 3T analog Sample and Hold, except the voltage decays and must be refreshed which consumes less space for high density DRAM but consumes more power due to the charge refresh rates putting in charge current. Newer DRAM's use 4 or 8 level voltages to store 2 or 3 binary bits for the highest density DRAMs. This requires a simple flash ADC/DAC to convert these levels in bits.
SRAM
SRAM's require at least 4T or 6T NFETs and use positive feedback of the cross-coupled NFETs as a flip flop with a weak drain pullup. Since one side is active LOW, it ensures under "most" conditions that this logic level remains static as long as power is applied ( Volatile)
The binary state is stored as complementary logic levels and read as a differential voltage from 2 other NFET gates when addressed going to a differential comparator or "sense amplifier"
SRAMs can be faster but more expensive since they require more transistors per cell.
S in SRAM means it is still Static.