I have a situation where it's possible a negative voltage may appear on the power supply rails driving CMOS chips. The negative voltage will be very limited in current, fed through a resistor.
The datasheets of course specify that Vdd should not go below ground by more than 0.3V.
Now of course, if you take the supply negative then the parasitic transistors and diodes begin to conduct – clamping the supply to 0.3-0.7V anyway.
My question is: how much negative current on the supply rails can a CMOS IC be expected to handle without failing or degrading? Would it be in the same sort of order as the clamping diode current for I/O pins (20mA)?
If it can't handle any significant negative current at all, then I'll have to install a schottky diode reverse across the power supply to clamp it below 0.3V.
I have seen numerous designs where there are ordinary silicon diodes across the power supply to protect against reverse bias. This seems to be pointless, since the datasheet says not to exceed 0.3V – not 0.65V. Surely the parasitic structures will conduct before the external silicon diode.
Best Answer
In order to have EOS protection diodes faster than the FET they are protecting they must be small and ESR , Imax, Pd are all related and inverse to speed.
These designed to protect against shoot-thru parasitic SCR effects in CMOS.
simulate this circuit – Schematic created using CircuitLab
Thus they use 2 diodes for each rail with 10k between them to make a better clamp and often specify not to exceed 5mA. If you cannot guarantee this then you must add more Schottky or TVS diode protection.
Faster logic may have even lower DC current limits. TI says 2mA www.ti.com/lit/an/slaa689/slaa689.pdf