Electrical – Assembler language basics parity flag

The parity and number of bits transmitted are controlled by the configuration of the UART (Universal Asynchronous Receiver/Transmitter) device in each piece of equipment. This component converts the data written to it in (usually) byte parallel format to the data bitstream that is sent serially between the client and server (in your example).

To transmit in 7E1 the UART is configured to ignore the MSB and then to add the parity bit as the last bit of data transmitted giving 8 transmitted data bits. In 8N1 the UART transmits the 8 data bits. By convention the data is transmitted LSB first.

Looking at your data I would suspect that where you have written B you really mean 8 (this would fit with the data transmission modes specified).

When transmitting the data over a 7E1 link then the 8 bits transmitted for your data will be

Data   Parity Transmitted byte
 06      0       0x06
 02      1       0x82
 05      0       0x05
 02      1       0x82
 0D      1       0x8D
 0A      0       0x0A

Are the three middle bytes ASCII representations of the values that you have declared in your question (2 ->0x32, 5->0x35 )? If this is the case than the data received will match the data transmitted with the addition of a parity bit.

Data   Parity Transmitted byte
 06      0       0x06
 32      1       0xB2
 35      0       0x35
 32      1       0xB2
 0D      1       0x8D
 0A      0       0x0A

I vote for DMA. It's really flexible in Cortex-M3 and up - and you can do all kind of crazy things like automatically getting data from one place and outputing into another with specified rate or at some events without spending ANY CPU cycles. DMA is much more reliable.

But it might be quite hard to understand in details.

Another option is soft-cores on FPGA with hardware implementation of these tight things.