Electrical – Biasing a cascode in a BJT differential pair

You want to use MOSFETs if you want maximum output resistance. Draw the small signal model and see for yourself. Try stacking N BJTs vs N MOSFETs to form Cascodes and see the limiting case for Rout. Because of a BJT's rpi, maximum output resistance is limited as you stack more and more stages. For MOSFETs the only practical limit is the voltage rails.

Edit: Clarification for the incorrect downvote

For BJT's forming cascodes by stacking ideal transistors it not that beneficial as the stack grows because the resistance rpi compromises the resistance boost of the cascode structure. So as the BJT cascode stack tends to infinity the output resistance tends to rpi and NOT infinity.

After actually building the thing

I can finally answer my own question in hindsight. I've built the circuit as featured in the question, with a 1:10 attenuator.

• Could I get away without impedance matching both ends of the coax...

  Yes, but signal integrity does suffer from doing so. The blue trace is a ~6 ns rise and fall time square wave (generated by a 74HC14-based relaxation oscillator) as measured with a standard 1:10 passive probe. In the first four screenshots the yellow trace is the output of the DIY differential probe, multiplied by 10 by the scope, as connected in the diagram. The last screenshot is the SMA connector being probed directly by another 1:10 passive probe. The scope is a 50 MHz Rigol DS1052E, with 1MΩ 15pF inputs.

  

  As can be seen, terminating both ends results in a clean signal without overshoot, but with only roughly 13 MHz of bandwidth. The fastest rise time is achieved by avoiding loading the opamp, indicating that a low load impedance slows the opamp down very severely.

• Are the BJT current sources fast enough to sink a constant 5 mA...

  Yes. The JFET buffers and their biasing current sources perform flawlessly when it comes to frequency response. The bandwidth is bottlenecked by the opamp choice.

• Is the addition of an inductor between the source of each JFET and the collector of the corresponding BJT a reasonable way of ensuring a constant JFET drain current...

  It wasn't necessary, so I didn't try. No idea.

• How sane is my PCB layout...

  I had no problems relating to the layout itself, but I absolutely should have designed the board with mounting to a shielded case in mind. Heat shrinking absolutely won't do, the very high impedance circuitry is very susceptible to all kinds of interference. Even moving my hand under the table the probe sits on affects measurements by capacitive coupling.

An unforeseen deficiency with my design is the inability to correct for output offset voltage. Turns out, JFETs are unique snowflakes: The Threshold voltage can vary by several hundreds of millivolts, even in transistors from the same batch. When I first built the probe, it output +600 mV with the probes shorted together. I unsoldered the JFETs, tested all that were in my parts box and soldered the two that best matched each other to the board. Now the offset is a smaller, but still significant +30mV. Future revisions should have a mechanism for compensating for this offset voltage with a trimmer pot.

Another problem is the input voltage range. Negative voltages are handled linearly down to -30 V and below, but positive voltages above +6 V (attenuated to +0.6 V) gradually induce more and more distortion. This is caused by the JFET source followers saturating as they hit the positive supply rail, exacerbated by the gate-drain threshold voltage of -2.1 V, which means that a 0 V input already causes a +2.1 V output.
The proper fix is to bias the attenuators to -2.1 V instead of ground.