Electrical – Clock Implementation Design Warning on Spartan 3E

clockfpgaspartanspartan-3xilinx

I am working with a SPARTAN 3E-FT256 on Xilinx 14.1, and have to generate a 25 MHz clock from the onboard 50MHz clock.I am accomplishing this with a Digital Clock Manager.

These are my UCF designations :

NET "CLK_50MHZ" LOC = "C8" | IOSTANDARD = LVCMOS33 ;   //GCLK 10
NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;              //DCM_X0Y1

DCM Instantiation :

wire clk_ibufg;
wire clock;
wire CLK0_OUT;

IBUFG clk_ibufg_inst ( .I(CLK_50MHZ) , .O(clk_ibufg) );
BUFG  clk_bufg_inst  ( .I(clock) , .O(clk));

ClockManager1 clock_converter (
.CLKIN_IN(clk_ibufg), 
.CLKFX_OUT(clock), 
.CLK0_OUT(CLK0_OUT)
);

I am very uncertain about the use of IBUFG and BUFG, but the datasheet seems to prefer the connections —IBUFG to DCM to BUFG—- for minimum skew.

The warning I get :

"The following Clock signals are not routed on the dedicated
global clock routing resources. This will usually result in
longer delays and higher skew for the clock load pins. This could
be the result of incorrect clock placement, more than 8 clocks
feeding logic in a single quadrant of the device, or incorrect
logic partitioning into the quadrant(s). Check the timing report
to verify the delay and skew for this net
Net Name: clock"

Is there any way to specify which BUFG or IBUFG to use? Why am I getting this warning?

Best Answer

Because you are using the CoreGenerator wizard, most of the low level stuff can be selected as part of the wizard meaning you don't need to instantiate them manually.

For the outputs, as you have selected auto, you don't need to add a BUFG. Otherwise the DCM will probably instantiate a BUFG for the output which then has to feed your BUFG (i.e. two in a row). Two global clock buffers shouldn't be placed in a row, firstly because there is no need to, and secondly because it means the signal has to leave the global clock network it is on from the first BUFG to get to the input of the second BUFG, hence your warning.

You should also be able to select that an IBUFG be used in the DCM wizard for the input, which means again, you need not instantiate it manually.

From the comments you also mention a warning about CLK0_OUT being unused. You have connected this output to a wire, and I can only assume that you are not then connecting it anywhere. CLK0 is used for feedback as you say, but according to the Xilinx App Note XAPP462 (pg10) you don't need feedback if using only the CLKFX output port, which in your case is true.

"No feedback. Allowed if using only the CLKFX or CLKFX180 outputs."

Related Solutions

Electronic – Working with Spartan-6 LX9 clock

Is there any documentation for that is generic or covers Spartan-6 LX9 board?

The DCM is fully contained within the FPGA chip. So it doesn't matter what board you have. The documentation will be based on what chip you have.

For the Spartan-6 family, see the Spartan 6 Clocking Resources User Guide
Is using this module is absolutely necessary in this example? Is that possible to do the same thing easily w/o using that module?

If you're just blinking LEDs, you probably don't need to use the DCM. Probably they used it because its a very complicated block and they specifically wanted to provide an example of using the DCM without much else in the way of complex logic to confuse things.
How people usually go about vendor specific things like clock? For example, if one wants to target both Altera FPGAs and Xilinx ones. What is the process to achieve that? Is it similar to ordinary C pre-processor typedefs etc?

Unfortunately, complex hard cores like clock management is one of the areas where there's not much compatibility between vendors. You'll likely have to make significant code changes if you want a design using these features that is portable between two device families, whether they're from the same or different vendors.

If you can simplify your interface so that you just have one input clock coming from off-chip, and a number of derived clocks that are distributed to the rest of your logic, the cleanest solution is probably to push all of the vendor-specific code into a single module that you can instantiate in your top-level code. Then you can just use a different "clock management" module depending which device you're targeting.

If you want to do something like dynamically changing the phase relationship between various clocks, or switch between several choices of reference clock frequency, you probably have no choice but to re-code substantial chunks of logic for different target devices.

Remember that in addition to the Verilog code, there will probably also be numerous constraints that need to be defined, and these will also need to be different for different devices.

Electronic – cannot fix: warning signal clk IBUF has no load please help!

Some hints for and questions to your code:

signal nextColor should not have a default value, because it's not mapped to a register
signal nextColor : color_type;
signal qtemp misses a default value: it's a counter/mapped to a register
secondly, this signal represents a counter and it's used in arithmetic calculations. So qtemp should be of type (un)signed or integer/natural. Doing artithmetic calculations on std_logic_vector is not a recommended style.
signal qtemp : unsigned(24 downto 0) := (others => '0');
qtemp should also be reset to 0 after 1 second passed by (as David Koontz wrote in the comment below)
if you change the type of qtemp you can rewrite the test (qtemp = "10111110101111000010000000") to (qtemp = 50000000)
Actually, it should be 49,999,999, because your counter starts at 0.
ONEsec_flag is asynchronous set and synchronous reset -> try to write full synchronous design.
line if (BaseBeat'event and BaseBeat = '1') and (ONEsec_flag='1') then can and will cause several problems:
1. BaseBeat is no clock signal, but you are using this signal as a clock. A better solution would be to use BaseBeat as an (clock)enable signal.
2. writing a rising edge condition and a clock enable in one line is no good style. Additionally it can cause synthesis tools to infer wrong hardware.
3. In combination with your else-statement this code will not be synthesizable. Here is a solution:
  
  calculating the flag (concurrent statement):
  ONEsec_flag <= '1' when (qtemp = 49999999) else '0'; -- ternary operator like ?: in C
  
  transition process:
```
transition: process(clk)
begin
  if rising_edge(clk) then         -- synchronous design using the main clock    
    if (BaseBeat = '1') then       -- using BaseBeat as an clock enable
      if (ONEsec_flag='1') then    -- using flag as an write enable (second ce)
        current_color <= next_color;
      end if;
    end if;
  end if;
end process;
```

So now, flag is calculated concurrently, it can be used to reset the second timer, otherwise a 25 bit vector will overflow after 2^25 cycles, that are 33554432:

process(clk)
begin
  if (clk'event and clk='1') then
    if (ONEsec_flag = '1') then      -- synchronous reset if one second is reached
      qtemp <= (others => '0');
    else
      qtemp <= qtemp + 1;
    end if;
  end if;
 end process;

this leads us to another problem: your counter signal has insufficient bits to hold 49,999,999 -> you need at least 26 bits
the UCF file has several errors:
1. NET "clk" ... has another signal name in comment
2. one signal can not have multiple locations
3. ON_BOARD_LED_output is a vector, so you should access each bit by using netname<index> and assign a location for each bit.
```
NET "ON_BOARD_LED_output<2>" LOC = "G1" ; # Bank = 3, Signal name = LD7
NET "ON_BOARD_LED_output<1>" LOC = "P4" ; # Bank = 2, Signal name = LD6
NET "ON_BOARD_LED_output<0>" LOC = "N4" ; # Bank = 2, Signal name = LD5
```
4. NET "output" ...: Why have you enabled internal pullup resistors (inside the IOB)? Most development boards have them externally.
5. and why are you limiting the current to 2 mA (DRIVE = 2)?
6. All pins have no assigned IOSTANDARD: This is needed for a proper timing analysis. If you want to switch to newer FPGAs and tools, it's then absolutely necessary to declare an IOSTANDARD

Best Answer

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Electronic – Working with Spartan-6 LX9 clock

Electronic – cannot fix: warning signal clk IBUF has no load please help!

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