Electrical – Closed-Loop Voltage Gain of Circuit Problem

You know the current through R4:

\$i_4 = \dfrac{A}{R_4}\$

Thus, you know the current through R3:

\$i_3 = i_4 \$

Thus, you know the output voltage of the 2nd op-amp:

\$v_{O2} = i_4(R_4 + R_3) = A(1 + \dfrac{R_3}{R_4})\$

Thus, you know the voltage across R2:

\$v_{R2} = A - v_{O2} = -A\dfrac{R_3}{R_4} \$

Thus, you know the current through R2 which is identical to the current through the capacitor:

\$i_C = i_{R2} = -\dfrac{A}{R_2}\dfrac{R_3}{R_4}\$

Now recall:

\$i_C = C \dfrac{dv_C}{dt}\$

Can you take it from here?

I can't find an error in my calcs, so I think I'm just misinterpreting what Vs and Is actually are.

Switching to the phasor domain, we have:

\$I_c = -\dfrac{A}{R_2}\dfrac{R_3}{R_4} = j \omega C V_c\$

or

\$V_c = -\dfrac{A}{j \omega}\dfrac{R_3}{R_2R_4C}\$

Thus, the output voltage of the first op-amp is:

\$V_{o1} = A + V_c = A - \dfrac{A}{j \omega}\dfrac{R_3}{R_2R_4C}\$

And the voltage across R1 is:

\$V_{r1} = A - V_{o1} = \dfrac{A}{j \omega}\dfrac{R_3}{R_2R_4C}\$

Finally, the current through R1 is:

\$I_{r1} = \dfrac{V_{r1}}{R_1} = \dfrac{A}{j \omega}\dfrac{R_3}{R_1R_2R_4C} \$

But the source current is identical to \$I_{r1}\$, thus:

\$\dfrac{V_s}{I_s} = \dfrac{A}{I_{r1}} = j\omega \dfrac{R_1R_2R_4C}{R_3} = j \omega L_{eq} \$

One analog approach is to add an Automatic Gain Control stage to the inverted signal path. The responsiveness of the AGC can be tuned to provide just enough tracking for the envisaged purpose.

If the AGC is placed early enough in the signal path, it will not need to handle much power, making design simpler.

This is a common enough requirement in analog-based noise cancellation designs that several manufacturers have published relevant app-notes about it. For instance, this page on Mouser might be a useful place to start reading up on it.

An AGC can be constructed using op-amps, Variable Gain Amplifiers (VGAs), or dedicated audio-use AGC ICs. The specific approach would be determined by preferences such as whether surface mount ICs are an option, and level of distortion that is acceptable.