Electrical – Deriving the NOT logic gate using PMOS logic


I recently started learning about Field Effect Transistors (FET's) and about the MOS circuit family. From my understanding NMOS is made from a p-type substrate and n-type source/drain, whereas the PMOS is made from a n-type substrate and p-type source/drain. However, I'm not so sure as to how we can derive different logic gates from PMOS and NMOS. Let's say we have the following diagram, where x and y are the inputs and z is the output:

Basic PMOS Diagram

The current in PMOS flows from the Source to the Drain terminal, and that can only happen if the Gate terminal is set to Low. Silly question, but why is that so? Furthermore, how can we use this to get the NOT logic gate (As shown in the second image)?

Best Answer

how can we use this to get the NOT logic gate

Consider this: -

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And this (for comparison between using NMOS and PMOS): -

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However, most commercial NOT gates use two transistor like this: -

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Or this if it helps a little more: -

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