Electrical – Designing a Silicon Photomultiplier Read-Out circuit

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I'm designing a Silicon Photomultiplier circuit with an amplifier. The base circuit can be shown below.

schematic

simulate this circuit – Schematic created using CircuitLab

This was from SensL's recommended circuit layout for their Silicon Photomultiplier, the MicroFJ-60035-TSV. However, this is for one photomultiplier. I designed a board with four photomultipliers, each with their own op amp circuit, but I was wondering, if I used 4 photomultipliers and had their output go to one op amp, would there be any design considerations to think about? You can see the proposed schematic below, though the -30V bias was left out since it would be the same as the previous circuit. At first, I thought that this would act like a summing amplifier, with each photomultiplier contributing a voltage to the op amp; depending on the output voltage, you can detect how many photomultipliers 'fired'. Does this idea seem reasonable, or is there something I'm not taking into consideration?

schematic

simulate this circuit

EDIT: Below is a revised circuit used in LTspice. I tried modeling the photomultiplier with a pulsed current source in parallel with a capacitor and resistor

schematic

simulate this circuit

Best Answer

Does this idea seem reasonable, or is there something I'm not taking into consideration?

Notice the 3 pF capacitor across the feedback resistor? This is normally chosen to counter the photodiode parasitic capacitance in order to constrain the noise gain of the opamp.

With four photodiodes in parallel, the feedback capacitance would need to rise four times in order to keep the noise back to where it was previously. That means you will also reduce the signal bandwidth to one-quarter.

Maybe you can live with this or maybe you can live with four times the background noise. Only you can say.