digital-logiclogic-gates
Would the sum of products expression look like so:
\$\overline{A}\cdot B+A\cdot\overline{B}=Z\$ ? And the corresponding circuit should look like so? 
Sorry for the bad drawing. I'm just wondering if this is how this concept works, but surprisingly this is not in any obvious google results.
Thanks for any help!
So Complement Law says \$\overline{\overline{X}} = X\$
We start with AND - OR. $$BD + \overline{A}B\overline{C} + \overline{A}CD$$ Double Complement. $$\overline{\overline{BD + \overline{A}B\overline{C} + \overline{A}CD}}$$ Use DeMorgan's Theorem to remove lower complement. $$\overline{\overline{BD} • \overline{\overline{A}B\overline{C}} • \overline{\overline{A}CD}}$$ AND - OR has become NAND - NAND. Use DeMorgan's on terms. $$\overline{(\overline{B} + \overline{D}) • (A + \overline {B} + C) • (A + \overline{C} + \overline{D})}$$ NAND - NAND has become OR - NAND. Use DeMorgan's Theorem to remove complement. $$\overline{(\overline{B} + \overline{D})} + \overline{(A + \overline {B} + C)} + \overline{(A + \overline{C} + \overline{D})}$$ OR - NAND has become NOR - OR. Double Complement again. $$\overline{\overline{\overline{(\overline{B} + \overline{D})} + \overline{(A + \overline {B} + C)} + \overline{(A + \overline{C} + \overline{D})}}}$$ NOR - OR become NOR - NOR. With an extra NOR connected as a NOT gate.
Following is the truth table for a sixteen-to-one demultiplexer.
A0 through A3 are the output address select inputs, and are used to steer the digital input signal on E1 bar to the output corresponding to the port pointed to by the address select inputs, as long as E2 bar is low.
If you need to construct the Boolean equation for each state, then all you have to do is to collect the terms required to make that state unique and relate them properly.
Best Answer
Your circuit diagram is correct.
Side note however, if you're designing logical transistors (i.e. CMOS logic), then you are able to reduce the amount of transistors it will take to produce an XOR gate. The amount you have above would take 16 NMOS and PMOS transistors. However, I contend that you can reduce this down to 10.