PWM frequency is 32 kHz so that's a period of about 32 us and half that time the transistor will be dumping energy into charging up those capacitor. It'll be doing it totally inefficiently too so maybe half that energy again is wasted in transistor heat.
Capacitor acquired energy is \$\dfrac{CV^2}{2} = \dfrac{2.2 \times 10^{-6}\times 144 }{2}\$ = 0.158mJ
BUT because charging the cap is done totally inefficiently, at a guess, the transistor will throw away just as much energy. It does this 32,000 times per second so that's a power of about 5 watts per transistor.
Now I may have over-egged this a bit by assuming that each 2.2uF would become totally discharged in one cycle of PWM but I'd wager that each transistor is doing over a watt just driving these capacitors back to full charge (32,000 times per second). Get rid of the caps and if you still have problems with noise then come back and tell us.
The lower the duty cycle the worse this will be because there will be a longer time for these caps to discharge and hence inefficiently re-acquire more of their 0.158mJ when the transistor switches back on again.
Is your transformer secondary 12 turns total or 12 turns on each side of the center tap? If it's the former, that's why you can only get 30 V under load. I calculate it this way:
Input voltage is 220 VRMS full-wave rectified to about 310 VDC.
This means that your half-bridge is driving the transformer with a voltage whose peak is half of this, or 155 V.
The 33:12 transformer is going to turn this into a peak voltage of about 56 V.
If the secondary is center-tapped, then you're only hitting the rectifiers with a peak of 28 V.
As for the excessive rise at low loads — well, that's why lots of SMPS specify a minimum load. It's actually quite difficult to design an efficient one that also has a huge dynamic range. One problem might be excessive leakage inductance (i.e., less than perfect coupling) in your transformer.
EDIT: Since I can't put this drawing in the comments, I'll add it here. Your transformer drive waveform always needs to be symmetric. At 50% duty cycle, it should look like a square wave, with a small amount of "crossover distortion" created by the dead time:
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-------- --------
But at lower duty cycles, it still needs to be symmetric, with longer "off" periods between the alternating pulses. It should look like this:
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- ------ ------ ------ --
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This is the sort of waveform that the drivers on the SG3525 are designed to produce.
Best Answer
In the question you say you want 4 A at 7 V (28 W), but in a comment 5 V at 10 A (50 W). That rules out cheap and available POE (power over Ethernet) transformers, which I often use for such things. Flyback transformers at the power levels you want are more scarce.
In any case, here are roughly the steps:
A trick I often use at this point is to set up a PWM output of a microcontroller to produce the switching pulses. If left open loop, this would make a little more voltage than you need under full load.
The trick is to use a shutdown input of the PWM module. Many micros have these. On the isolated side, drive a opto-coupler when the voltage hits the regulation threshold. On the primary side, this activates the shutdown input of the PWM. Make sure the PWM recovers when the shutdown signal is no longer asserted. Basically, that kills the oscillations when the voltage gets to where you want it, then resumes them when it drops below the threshold. This all happens in hardware with 0 CPU intervention after initialization.
This method results in a little more ripple than something that carefully and smoothly adjusts the PWM duty cycle in a control loop, but its a lot simpler and very robust.
I'm doing this in one of my current projects. In this case I need isolated 5 V for some communication interfaces. I use a PNP transistor around a 5 V LDO to sense when the LDO input is the B-E drop above its output. 700 mV or so is a nice comfortable headroom for this LDO. The transistor ultimately drives the feedback opto, which then shuts down pumping power into the isolated section. There is about 100 mVpp ripple on this input to the LDO, but the output is quite flat.
Here is a snippet of a schematic that implements what I described above:
Q5 is the switch, which is driven from the PWM output of the micro via a FET gate driver. The basic power supply on the isolated side is the secondaries of TR3, D6, and C23.
IC7 is the LDO that makes the clean and regulated 5 V power. Q6 is connected in such a way that it turns on when the input of the LDO gets to about 700 mV above its output. That in turn turns on opto IC8, which activates the shutdown input to the PWM, which stops dumping power to the isolated section. Eventually the voltage drops to where the LED in the opto is no longer on enough to keep the PWM off, and power is again transferred to the isolated section.
The input of the LDO has about 100 mVpp ripple on it, which is cleans up nicely to make its regulated output of 5 V.
Note that you can sometimes use the rougher 5.7 V supply directly. In this case I have a couple of LEDs, which actually take more power than most everything else. I have the LEDs connected to their current comes from the 5.7 V supply, thereby requiring less current out of the LDO. The extra 700 mV gets wasted as heat either way, but this way distributes it instead of concentrating it in the LDO.