I understand that with synchronous FPGA, the whole execution is done in cycles. What happens when my circuit has two parts which give outputs in different cycles (one has greater depth than the other) and I need the outputs in a different part of the circuits in a single cycle? Is there any better way than just adding logic gates which do nothing in order to get delay of the required number of clock cycles?
I know that I usually don't have to care about this when programming FPGA's, but I would like to understand it.
Best Answer
You would use either pipeline registers or FIFOs to take up the delay. Pipeline registers are good for short delays, and you essentially get one cycle of delay per stage. At their simplest, they act like shift registers, but it is also possible to have handshaking between stages. FIFOs are good for longer delays. A FIFO will store the data in an internal RAM for the duration of the delay. Another advantage of a FIFO is that it can cross clock domains.