While working with the CD4000.lib in LTSpiceIV I came across the following:
A capacitor was discharged via a CMOS Schmitt trigger input. Analysis of this behavior revealed that LTSpice may not handle hidden pins correctly.
See for yourself:
The first case was the one where I noticed the behavior.
In the second case, I represented the discharge as an RC element.
In the third case I looked at the input filter stage of the CD40106 in the CD4000.lib (there is also a 100Meg resistance against VGND as expected. ) The net list of the subckt CD40_IN_S_1 was transferred into the current simulation and connected to GND and VDD.
During the simulation, of course (as it should be) the diodes struck and cut the negative voltage.
In the fourth case, input filter stage has been inserted again, but this time without connecting the diodes to VDD and GND.
During the simulation, exactly the behavior that caused me headaches became apparent.
This raises questions:
- What's wrong here?
- How are hidden pins used in LTspice?
- What has to be done in this case to get correct simulation results with the CD4000.lib?
Here is the asc file:
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Version 4
SHEET 1 3772 2028
WIRE -48 320 -352 320
WIRE 48 320 -48 320
WIRE 192 320 112 320
WIRE 400 320 192 320
WIRE 640 320 400 320
WIRE -352 496 -352 320
WIRE -48 496 -352 496
WIRE 48 496 -48 496
WIRE 192 496 112 496
WIRE 400 496 192 496
WIRE 656 496 400 496
WIRE 768 496 736 496
WIRE 560 624 560 576
WIRE 560 704 560 624
WIRE -352 864 -352 496
WIRE -48 864 -352 864
WIRE 48 864 -48 864
WIRE 192 864 112 864
WIRE 400 864 192 864
WIRE 560 864 560 768
WIRE 560 864 400 864
WIRE 672 864 560 864
WIRE 736 864 672 864
WIRE 928 864 816 864
WIRE 672 912 672 864
WIRE 928 912 928 864
WIRE 560 944 560 864
WIRE 112 992 -240 992
WIRE 144 992 112 992
WIRE -240 1040 -240 992
WIRE 672 1056 672 992
WIRE 784 1056 672 1056
WIRE 928 1056 928 976
WIRE 928 1056 784 1056
WIRE 560 1104 560 1008
WIRE 784 1104 784 1056
WIRE -240 1136 -240 1072
WIRE 96 1136 -240 1136
WIRE 144 1136 96 1136
WIRE -240 1168 -240 1136
WIRE 784 1168 784 1104
WIRE 560 1328 560 1264
WIRE -352 1488 -352 864
WIRE -48 1488 -352 1488
WIRE 48 1488 -48 1488
WIRE 192 1488 112 1488
WIRE 400 1488 192 1488
WIRE 560 1488 560 1392
WIRE 560 1488 400 1488
WIRE 672 1488 560 1488
WIRE 736 1488 672 1488
WIRE 928 1488 816 1488
WIRE 672 1536 672 1488
WIRE 928 1536 928 1488
WIRE 560 1584 560 1488
WIRE -352 1632 -352 1488
WIRE 672 1680 672 1616
WIRE 784 1680 672 1680
WIRE 928 1680 928 1600
WIRE 928 1680 784 1680
WIRE 560 1696 560 1648
WIRE -352 1728 -352 1664
WIRE 784 1728 784 1680
WIRE 784 1792 784 1728
FLAG -48 496 stimulus
FLAG 192 496 response2
FLAG 192 320 response1
FLAG 192 864 response3
FLAG 768 496 0
FLAG -240 1168 0
FLAG 784 1104 VGND
FLAG 112 992 VDD
FLAG 96 1136 VGND
FLAG 560 1104 0
FLAG 560 624 VDD
FLAG -48 320 stimulus
FLAG -48 864 stimulus
FLAG -352 1728 0
FLAG 192 1488 response4
FLAG 784 1728 VGND
FLAG -48 1488 stimulus
SYMBOL cap 48 512 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C1
SYMATTR Value 2.2n
SYMBOL cap 48 336 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C3
SYMATTR Value 2.2n
SYMBOL diode 576 1008 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value CD40DIO1
SYMBOL diode 576 768 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMATTR Value CD40DIO1
SYMBOL res 720 848 M90
WINDOW 0 5 56 VBottom 2
WINDOW 3 27 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL cap 944 912 M0
SYMATTR InstName C4
SYMATTR Value {Cval}
SYMBOL res 656 896 R0
SYMATTR InstName R2
SYMATTR Value 1e8
SYMBOL cap 48 880 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C5
SYMATTR Value 2.2n
SYMBOL Dig_Add\\CD4xxx\\cd40106b 688 272 R0
WINDOW 38 -118 145 Left 2
WINDOW 39 -118 117 Left 2
SYMATTR InstName U2
SYMATTR SpiceLine VDD={Versorgungsspannung} SPEED={SPEED} TRIPDT={TRIPDT}
SYMBOL res 640 512 R270
WINDOW 0 27 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 100Meg
SYMBOL MiniSyms4\\voltage- -240 1056 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value {Versorgungsspannung}
SYMBOL MiniSyms4\\voltage- -352 1648 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE({Versorgungsspannung} 0 0.025 0.0001)
SYMBOL res 720 1472 M90
WINDOW 0 5 56 VBottom 2
WINDOW 3 27 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL cap 944 1536 M0
SYMATTR InstName C2
SYMATTR Value {Cval}
SYMBOL res 656 1520 R0
SYMATTR InstName R5
SYMATTR Value 1e8
SYMBOL cap 48 1504 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C6
SYMATTR Value 2.2n
SYMBOL diode 576 1648 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D3
SYMATTR Value CD40DIO1
SYMBOL diode 576 1392 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D4
SYMATTR Value CD40DIO1
TEXT -312 584 Left 2 !.param Versorgungsspannung=15\n.param SPEED=1.0\n.param TRIPDT=5e-9
TEXT 672 784 Left 2 !.MODEL CD40DIO1 D(Is=1e-12 Rs=100)
TEXT 976 880 Left 2 !.param Cval = 1.8e-12*5/{Versorgungsspannung}*{SPEED}\n.param vt1=2.5/5\n.param vh1=0.4/5\n.param gain=(1/{Versorgungsspannung})
TEXT 664 624 Left 4 ;Schmitt-input; 2.9V/2.1V @5 CD40_IN_S_1
TEXT 1408 1144 Left 2 ;see CD4000.lib
TEXT -204 1750 Left 2 !.tran .5
TEXT 440 848 Left 2 ;in
TEXT 440 1472 Left 2 ;in
TEXT 864 1472 Left 2 ;out10
TEXT 872 848 Left 2 ;out10
TEXT 912 320 Left 2 ;cd40106b.asy is linked to cd4000.lib
TEXT 656 416 Left 2 ;should be hidden pins ( see parameter window: "SpiceModel VDD 0"
TEXT 672 688 Left 2 ;input filter part \nreengineered from .subckt CD40106, .subckt CD40_IN_S_1
TEXT -304 928 Left 2 ;Here (hidden) pins are explicitly connectet to VDD and VGND
TEXT 1048 1080 Left 2 ;response3 is clamped by diodes D1, D2.
TEXT 904 480 Left 2 ;RC with Tau=2.2n*100Meg gives the same response\n--> where are these 100Meg's ...
TEXT 712 1000 Left 2 ;...here.
TEXT 680 1248 Left 2 ;without diodes: response4 = response2
TEXT 680 1328 Left 4 ;What is wrong with case 1 and case 3
TEXT -256 288 Left 4 ;case 1:
TEXT -288 824 Left 4 ;case 3:
TEXT -264 456 Left 4 ;case 2:
TEXT -264 1448 Left 4 ;case 4:
RECTANGLE Normal 1632 1168 400 576 2
RECTANGLE Normal 1632 1792 400 1200 2
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Best Answer
You must DC bias to Vdd/2 whenever AC coupled