4700Ω on the gates of the MOSFETs is far too high. These should be no more than about 100Ω.
With such a high resistance, the MOSFETs are switching far too slowly and dissipating way too much power, especially when the motor isn't actually running yet and passing its "stall" current.
Also, what is C2 in there for? Probably should be deleted.
One more thing: Although the body diodes on the MOSFETs will protect them somewhat, it would probably be better to add a beefy freewheel diode directly across the motor.
The calculation method is close enough to OK to be OK.
But you may have made a very bad assumption re required switching speed.
Examination of your formula and situation will make it clear that the current is the average gate current while the gate capacitor is charging (OR discharging).
The average current = Q.f = Ig.t.f
where t is charge time and f is number of gate turn-ons/second.
The LMx17xx family are not LDOs by any normal meaning of the term. It's probably not too important here.
As above, the figures for current is mean current during turn on.
IF you turned the MOSFET on at 50 kHz and
turn on time = 200 nS
and I_gate_average = 1A
Then
Imean = Ig.t.f = 1 x 2E-7 s x 50000 = 10 mA average.
A suitably sized capacitor at the regulator output would probably suffice and allow the regulator to be very understressed.
Be sure that when you say 50 kHz you mean that that is the number of times per second that the FET is turned on.
Also note that at 50 kHz your PWM "frame period" = 1/50 kHz = 20 uS BUT if your PWM can run down to 1% duty cycle then an on time for the shortest bit is 20 uS/100 = 0.2 uS = your design charge time.
Tmin_on = 1/frame_frequency x minimum_duty_cycle.
Why are you using the HV part?
usually the regulator is fed from a supply slightly above Vout.
In most cases the HV part would be over over kill.
If it is needed it suggests that you are trying to do something "tricky".
Be sure your MOSFET gate can tolerate 15V.
Put a reverse biased zener gate to source close to MOSFET with minimum lead and track lengths. Vzener > Vgate_drive_max and < to << Vgate_abs_max. This clamps the gate safely against eg Millar capacitance drain transients. Theoretically not needed with pure resistive load. I ALWAYS fit one. Certainly a good idea with an inverter.
Overkill - reverse biased small Schottky gate to source same as zener. If gate rings the SChottky clamps negative half ringing cycle and eats ringing energy.
Be sure to have turn off gate drive that is about as aggressive as turn on drive.
Best Answer
You have made the calculations so you should know what Rdson is required. For 12V supply a 25V VGS and 30V VDS rating will be sufficient (higher voltage FETs generally have higher RDSON and so should be avoided). To find suitable FETs, use the parametric search function on your vendor's website.
Alternatively you could wire two or more weaker FETs in parallel to reduce total RDSON and also increase dissipation capability. Two packages have twice the surface area so they can dissipate (almost) twice as much power, and since each is carrying only half the total current it dissipates 1/4 the power of a single (same spec) FET. Of course they will also take up more space, but may still be more compact than a single FET with heatsink.
However low RDSON comes with a price - high Gate charge. The circuit in your link will probably not be suitable because it has very weak Gate drivers. If you are using PWM the low-side FETs will need to be switched on and off rapidly to avoid excessive power dissipation during the transition period (when the FET is carrying both high voltage and high current at the same time). You need high current drivers that can charge and discharge the Gates quickly.
You can make a high current Gate driver with discrete transistors, or just use an IC such the TC1428 (which has both inverting and non-inverting drivers, so you only need two ICs to drive all the FETs).