I'm pretty confident in this circuit theoretically, but I wanted to run it past the EESE community in case there is some flaw in the design, maybe someone could point it out. If it's great, then the question makes a good reference for others seeking a similar solution.
So my design constraints are I would like to be able to switch up to about 350mA at 5V, and I would like the control signal to this switch to be 5V and active-high. That is to say, when 5V is applied to the control, the switch should be closed and allow current to pass, and when 0V is applied to the control, the switch should be open, and no current should flow into through. Default state should be off if control input is floating.
The circuit I have conceived for this purpose is pretty basic.
simulate this circuit – Schematic created using CircuitLab
… and I've identified a dual-FET package that should more than cover my requirements DMG6602SVT.
Any problems with this concept?
Best Answer
It will work okay.
The speed switching off will be much slower than switching on because the 10K resistor has to supply the ~6nC of gate charge on the p-MOS transistor. Maybe 10's of microseconds, but that should be okay at relatively low current- if you refer to the SOA curve. And relatively infrequent switching (not many kHz PWM).
Another possible gotcha is that if the switch is activated with the 5V power rail lower than normal then it's possible for the p-channel MOSFET to turn partially on and damage or unsolder itself. If you are driving it with a processor that has brownout reset and can verify that the pin goes low or high impedance under reset conditions it should be fine.
Edit: You might also want to add a diode from the output to ground in case there is significant inductance in (or in the wires to) the load. The slow 'off' switching will help with this, but with enough inductance the drain could go far enough below ground to avalanche the 30V output MOSFET.