capacitordigital-logic
I'm trying to find the time constant of this digital circuit. It's one of the first digital circuit I'm dealing with, so I don't really know how to deal with logical ports.
What would be the equivalent impedance of this circuit and how to find it? I know the basic rules to apply to find it (turn off current/voltage sources) but I don't know how to do it when logical ports are present.
Thanks!
simulate this circuit – Schematic created using CircuitLab
To simply understand the circuit you can locate a proper ground point to use as a reference for calculations and transformations of the circuit. In case of the oscilloscope, you can take one of it's connectors as the ground and split the circuit to make it easier to digest.
Given the oscillograph connections, you can transform the circuit to look like this. Does it make more sense this way?
simulate this circuit – Schematic created using CircuitLab
Try simulating it and measure the time constant from the graph, then calculate what it should be. The time constant tau is the time which it takes for the voltage to rise or fall to $$V_{initial}+(1-\frac{1}{e})\times(V_{final}-V_{initial})$$ where \$V_{initial}\$ is the stable voltage before the switching and \$V_{final}\$ is the voltage after the switching. So if before the switch it was 0 and after the switch it is 1, the time constant will be the time it took for the voltage to rise to ~0.63V.
Try replacing the capacitor with an inductive coil and see what happens in the time simulations to answer your last question thoroughly. Remember that$$ \tau = R \times C= \frac{L}{R}$$
You could try to use Laplace transform.
Consider the following equivalent circuit:
simulate this circuit – Schematic created using CircuitLab
This is the situation in the Laplace domain when your circuit has the generator off, i.e. shorted, and the caps were charged at 4V. Note the two 'initial condition' generators, that's \$\frac{4V}{s}\$, while for the capacitance value is \$\frac{1}{sC}=\frac{1}{s\cdot 10n}\$. The unit is not Farad, as the schematic tool suggests.
Now you can solve the circuit with the usual linear circuits tools, a good idea might be superimposition, then find \$V_x(s)\$. If you're lucky enough you may even be able to anti transform it and come up with the time domain funcion.
If you don't know what the Laplace transform is you can just write all node voltages as a function of the currents, keeping in mind that in a cap \$i=C\dot{v}\$ and throwing in the initial conditions when you integrate. Or you could just learn to use the L-transform that is basically syntactic sugar for differential equations.
Best Answer
For the ideal gates case the situation looks something like this:
When we first apply a positive trigger pulse to the input of a NOR gate, the output of the first NOR gate goes LOW. And this starts the process of charging the capacitor.
After some time when the voltage across the capacitor reach the NOT gate threshold voltage (0.5Vdd = 2.5V for Vdd = 5V). The NOT gate will change his output stage from high to low. And this will cause the first NOR gate to switch his output from low to high.
And this change in NOR gate state will start discharge process, the capacitor start to discharge through resistor R and P channel MOS built-in in the first NOR gate.
I would like to add that in real life the voltage at the second gate input don't reach 7.5V This is because all CMOS and TTL gates has a input diode protection circuit. And this protection circuit reduce the gate input voltage to about 5.7V. And there will be additional discharge current flow through input protection diode. This input protection diode is connect parallel to R1 resistor.
As for the time constant
$$T = RC*ln(2) \approx RC*0.7$$
http://www.doctronics.co.uk/DDE/DDE_04.html#NOR