Electrical – How to create AND/OR logic gates using comparators

Here's your circuit:

^{simulate this circuit – Schematic created using CircuitLab}

Please note that since the high side mos are P mosfets they are on when the input is low.

How did I draw that? First of all you need to fill the truth table, then you build the pull down network, i.e. the NMOS part, and the pull up network separately.

Let's make the table:

A    B    F
0    0    1
0    1    1
1    0    0
1    1    1

Inspecting the table you can see that the output is low when A=1 and B=0. Your pull down network will consist of two series (logical AND) transistors, one connected to A, the other to /B.

The output is high if A=0 or (A=1 and B=1). Note that here I have already simplified the formula (search for karnaugh maps, minterms, maxterms, product of sum, sum of product).

Your pull up network will consist of the parallel (logical OR) of:

• the series (AND) of two transistors, one connected to /A, the other to /B
• a single transistor connected to A

Note that i inverted the signals for the pull up network because P mos turn on when input is LOW.

I'll start by pointing out that your code is probably faulty. The last IF statement should examine switch 1 and switch 3, not 1 and 2.

With that said, let be restate your requirements:

1) If either SW2 or SW4 are open, start filling the tank (turn on the motor).

2) When both SW1 and SW3 are open, stop filling the tank (turn off the motor).

Right? And you do realize that this may cause one tank to overflow while the other tank is filling, right?

In this case, as @on8tom has pointed out, you need some sort of storage device, and a set/reset flip-flop is an excellent choice. Then

^{simulate this circuit – Schematic created using CircuitLab} should do what you want. Note that I've added a flyback diode on the relay coil, and you should always do this. The diode should be rated for more current than the relay coil draws.