Electrical – How to implement a digital clock in Logisim

fpgalogisim

I'm trying to simulate a 12h-digital clock in Logisim. Here's the logic diagram:

I could simulate BCD to 7 Segment but I don't know how to create a CTR DIV 10 and CTR DIV 6 in Logisim, so I tried to look into some logic diagram and found this:

By the way, here's the structure of the CTR DIV 10 but I don't understand how it works:

And here's my approach to this implementation:

Any help to simulate this, thanks in advance.

Best Answer

Still not sure what your question is, but I try to answer what I have understood.

I suggest to make two part of simulating CTR DIV 10

Create the model of 74F162 (aka. a general purpose counter)
Add the overflow logic. (to make the DIV 10)

1. Create the model of 74F162

There are so many detailed counter implementation post like this or this.

2. Add the overflow logic

To create a counter with custom modulo (period) you need to add the overflow/reset logic. This circuit will reset your counter when your counter reach the wanted maximum. (10 at DIV 10 and 6 at DIV 6). Lets do the 10: You need to detect the binary 1010 (which is the decimal 10).

schematic

^{simulate this circuit – Schematic created using CircuitLab}

The output of the circuit above will be high only when the input is decimal 10. You can connect this circuit to reset input of your counter. (Note the polarity, your counter maybe have active low reset input.)

Related Solutions

Electronic – Digital Circuit with Toggle Switch using Logisim

It looks like your latches woke up in the unknown 'X' state, and the complement of X is another X. For your simulation to work you need a way to initialize the latches in a valid logic state, either 0 or 1. Sorry, but I'm not sure how to do this in Logisim other than adding a separate reset input to your circuit. Perhaps you can specify an initial state in the properties for each gate.

Of course, in real life the latch will wake up in either a 0 or a 1 state and the toggle will work as expected. This is a common artifact of digital logic simulations...unknown values propagate pessimisticly...and you soon learn that it's best to have an explicit reset for the storage elements.

Using Digital Clock Manager with Verilog to generate 25Mhz clock from 32Mhz internal clock

The Instanitation template gives you an example of how to use the core in your project. All you need to do is paste it into your verilog file.

// Instantiate the module
DCM32to50 instance_name (
    .CLKIN_IN(CLKIN_IN), 
    .CLKFX_OUT(CLKFX_OUT), 
    .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), 
                         ^ Change the signals in brackets to your signals
     ^ You don't need to change the port names
    .CLK0_OUT(CLK0_OUT)
);

To help you match it up with the tutorial, in VHDL, it looks like this:

DCM32to50_i : DCM32to50 
port map (
CLKIN_IN        => CLKIN_IN,
CLKFX_OUT       => CLKFX_OUT,
CLKIN_IBUFG_OUT => CLKIN_IBUFG_OUT,
CLK0_OUT        => CLK0_OUT);
                         ^ Signal name you can make what you want.
  ^ Port name doesn't change

CLKIN_IN is your input 32 Mhz clock
CLKFX_OUT is the new 25 Mhz clock
CLKIN_IBUFG_OUT is a buffered version of your 32 Mhz clock
CLK0_OUT is your input clock at 0 phase (basically your input clock again).