# Electrical – How to limit the output voltage of a TCXO

circuit-designclockoscillatortcxo

I am using an SiT1552 MEMS TCXO providing 32.768 kHz. It will be sourcing two ICs: a microcontroller and a DA14580 Bluetooth Low Energy transceiver.

The ICs and TCXO are all powered by 3.3V. The TCXO output is the standard 10%-90% LVCMOS voltage swing. It can drive up to 100 pF. It is not AC-coupled.

The MCU is happy with this voltage swing. It wants ~50% duty cycle.

The BLE clock input, however, is internally AC-coupled and needs a 0.1 – 1.5V (pk-pk) voltage swing.

In an app note which requires registration to view, it suggests to use a series capacitor for attenuation:

I can do this with a larger cap so as to attenuate the signal even more. The TCXO can handle the extra load.

Here is the result.

• Does it look sane?
• Will the MCU remain happy?
• Is there a better method?

.

simulate this circuit – Schematic created using CircuitLab

No, you want a smaller value series capacitor (higher impedance) in order to get more attenuation.

For example, if you use a 6.8 pF series capacitor with the load capacitance of 6-9 pF, you'll reduce the signal amplitude to about half its original value.

If you're trying to reduce a 3.3Vpp to less than 1.5Vpp, you'll want an even smaller value. If the load capacitance is just 6 pF (worst case), then the series capacitor should be no larger than 5 pF. Try 4.7 pF (next lower standard value).

Otherwise, looks fine.

Of course, these values are very tiny, to the point where parasitic capacitances could seriously affect the results. To mitigate this, you could add an additional external capacitor in parallel with the input capacitance of the BLE chip:

simulate this circuit – Schematic created using CircuitLab

Note that this arrangement still limits a 3.3Vpp input to 1.5Vpp going to the BLE chip. The source sees a net capacitance of a little more than 15 pF to ground as its load.