Electrical – I2C Master communication with a Ten bit slave

I have a doubt related to 10-bit mode of I2C protocol for multiple transactions with repeated start:

I would like to know how an i2c master / slave has to be designed to support 10 bit addressing for multiple transactions with repeat start (say to change the direction of the transfer) in between transactions.

Following is the scenario :

start + Read from a ten bit slave + repeat start + write to a ten bit slave + stop

As per I2C protocol,

• Master-transmitter transmits to slave-receiver with a 10-bit slave
  address. When a 10-bit address follows a START condition, each slave
  compares the first seven bits of the first byte of the slave
  address (1111 0XX) with its own address and tests if the eighth
  bit (R/W direction bit) is 0. It is possible that more than one
  device will find a match and generate an acknowledge (A1). All
  slaves that found a match will compare the eight bits of the
  second byte of the slave address (XXXXXXXX) with their own
  addresses, but only one slave will find a match and generate an
  acknowledge (A2). The matching slave will remain addressed by
  the master until it receives a STOP condition (P) or a repeated
  START condition (Sr) followed by a different slave address.

• Master-receiver reads slave-transmitter with a 10-bit slave address.
  The transfer direction is changed after the second R/W bit. Up to and
  including acknowledge bit A2, the procedure is the
  same as that described for a master-transmitter addressing a
  slave-receiver. After the repeated START condition (Sr), a matching
  slave remembers that it was addressed before. This slave then checks
  if the first seven bits of the first byte of the slave address
  following Sr are the same as they were after the START condition (S),
  and tests if the eighth (R/W) bit is 1. If there is a match, the
  slave considers that it has been addressed as a transmitter and
  generates acknowledge A3. The slave-transmitter remains addressed
  until it receives a STOP condition (P) or until it receives another
  repeated START condition (Sr) followed by a different slave address.
  After a repeated START condition (Sr), all the other slave devices
  will also compare the first seven bits of the first byte of the slave
  address (1111 0XX) with their own addresses and test the eighth (R/W)
  bit. However, none of them will be addressed because R/W = 1 (for
  10-bit devices), or the 1111 0XX slave address (for 7-bit devices)
  does not match.

From the scenario that i mentioned above, the first transaction (read) can be implemented as mentioned in the spec. Once there is a repeat start on the bus for second transaction, master has to put (11110xx0) for second transaction i.e. master write. But there can be many devices on the bus with the same 2 MSB bits which acknowledges it.
How can this scenario be handled ?

Also wanted to know how to perform a write followed by a read transaction with the repeated start for the same ten bit slave ?? (after repeated start (which comes after first transaction), are we supposed to send all 3 address bytes or only 11110xx1 address byte is enough).

Thanks in advance.