Electrical – Is it necessary to have a finite state machine for every filter you write in VHDL

filterfpgavhdl

I have recently coded a filter in VHDL to be synthesized for an FPGA and I did it using the conventional method where you first design the finite state machine(FSM) and then implement it in your code. But I realized that when I reduced the number of states in the FSM by combining a few states, the filter worked much faster. So, in an attempt to maximize the speed of computation, if I just write the entire filter inside a process so that all the statements get executed sequentially, will it affect the computation in any way?

Best Answer

Depends on how you want to build your filter. The real questions are these: what sample rate do you need, and how long is your filter? If your sample rate is low, then you can get away with an FSM driven design that can use many clock cycles to produce each output sample. It's certainly a good idea to make the FSM as efficient as possible, though. No sense on wasting extra cycles doing nothing, though it may make sense to do some pipelining so you can run at a high clock speed and get timing closure more easily. If your sample rate is high, then you can't spare the clock cycles and will have to implement more parallelism, probably in the form of some sort of pipelining. If your sample rate is so high that you need to process multiple samples on each clock cycle, then you need to do some pretty careful pipelined design.

Related Solutions

VHDL Finite State Machine Pattern Checker

There are several issues with your code. My rewritten version is below.

The main problem is that your code was that the assignment of Z was incorrect. The next problem was that the state machine itself was incorrect. As it was written, Z should have gone high after a pattern of "11", and not "110". It also would have gotten stuck in state S2 and not recovered.

I should also mention that there were several "stylistic" issues with your code too. Having two processes instead of one was a major one. I cleaned up that as well. This allowed for having only a single state signal, which makes the whole thing more readable as well.

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

 entity checker is
   Port ( clk : in  STD_LOGIC;
            x : in  STD_LOGIC;
            z : out STD_LOGIC);
 end checker;    

 architecture Behavioral of checker is    
   type state_type is (S0, S1, S2);
   signal state: state_type := S0;
 begin

     process(clk)
     begin
       if rising_edge(clk) then
         case state is 
             when S0 => 
                z <= '0';
                if x='1' then 
                  state <= S1;
                else 
                  state <= S0;
                end if;

             when S1 => 
                z <= '0';
                if x = '1' then 
                  state <= S2;
                else 
                  state <= S1;  -- S1, not S0 because we also want to detect a "111...1110" 
                end if;

             when S2 => 
                if x = '0' then
                  state <= S0;
                  z <= '1';  -- Z='1' only when a match is made
                else
                  state <= S0;  -- Goes back to S0 to detect the next pattern
                  z <= '0';
                end if;

             when others => 
                z <= '0';
                state <= S0;  -- In case the state machine is in an invalid state 
         end case;
       end if;    
     end process;

   end Behavioral;

Update: Here's a rewritten testbench:

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture arch_testbench of testbench is
  component checker
    port (clk   :in  std_logic;
          x     :in  std_logic;
          z     :out std_logic);
  end component;

  signal clk    :std_logic := '1';
  signal x      :std_logic := '0';
  signal z      :std_logic := '0';

  signal sr     :std_logic_vector (15 downto 0) := "0001100011111110";
begin

  process (clk)
  begin
    if clk='1' then
      clk <= '0' after 5.0 ns, '1' after 10 ns;
    end if;
  end process;


  process (clk)
  begin
    if rising_edge(clk) then
      sr <= sr(sr'high-1 downto 0) & "0";
    end if;
  end process;

  x <= sr(sr'high);

  UUT:  checker
      port map (clk, x, z);

end arch_testbench;

Call a Finite State Machine in VHDL

A FSM is a sequential piece of circuitry, and functions are combinational only, so a function cannot represent by itself a FSM. However, the combinational paths of the FSM can be represented with functions. Typical examples are coding the next state or the outputs based on the current state and inputs. It is a very clean way of coding a FSM.

A procedure, on the other hand, can contain sequential statements, but when they do they are mostly used for testbenches using wait statements, which are not synthesizable.

Best Answer

Related Solutions

VHDL Finite State Machine Pattern Checker

Call a Finite State Machine in VHDL

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