Electrical – Is it possible to generate internal reset pulse in verilog with machxo3lf fpga

latticeresetverilog

I have a board without Reset input for my design. But I need to reset at fpga startup.
Is there a verilog solution to generate this pulse ?

Best Answer

The datasheet on MachXO says that

The MachXO registers in PFU and sysI/O can be configured to be SET or RESET. After power up and deviceconfigured, the device enters into user mode with these registers SET/RESET according to the configuration set- ting, allowing device entering to a known state for predictable system function.

Therefore, the simplest thing you can do is to configure all regs that need to be initialized with initial verilog construct or the equivalent understood by the tools.

If you still need a 'traditional' reset pulse, you can do it like this:

reg [3:0] rst_cnt;

wire rst_n = rst_cnt[3];

initial rst_cnt=4'd0;

always @(posedge clk)
if( !rst_n )
    rst_cnt <= rst_cnt + 4'd1;

This code again relies on the ability to set initial (power-on) values for the flipflops of MachXO.

Related Solutions

Electronic – Reset signal for fpga evaluation board

With an FPGA you can make use of the fact that your flipflops will initialise to a known state and create an internal synchronous reset signal which you can "and" with the external one.

When using an external reset, make sure that you synchronise it to the internal clock (with a different synchroniser for each clock if you have more than one) otherwise you may find that your logic comes out of reset in weird ways. This is because the signal will have different delays to different parts of your circuit and if the reset button is released just before a clock edge, some parts of the FPGA will see it (as the reset signal made it to them before the clock signal) and other parts will see it one clock cycle later (as the reset was slightly delayed and therefore missed the clock edge).

Using Digital Clock Manager with Verilog to generate 25Mhz clock from 32Mhz internal clock

The Instanitation template gives you an example of how to use the core in your project. All you need to do is paste it into your verilog file.

// Instantiate the module
DCM32to50 instance_name (
    .CLKIN_IN(CLKIN_IN), 
    .CLKFX_OUT(CLKFX_OUT), 
    .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), 
                         ^ Change the signals in brackets to your signals
     ^ You don't need to change the port names
    .CLK0_OUT(CLK0_OUT)
);

To help you match it up with the tutorial, in VHDL, it looks like this:

DCM32to50_i : DCM32to50 
port map (
CLKIN_IN        => CLKIN_IN,
CLKFX_OUT       => CLKFX_OUT,
CLKIN_IBUFG_OUT => CLKIN_IBUFG_OUT,
CLK0_OUT        => CLK0_OUT);
                         ^ Signal name you can make what you want.
  ^ Port name doesn't change

CLKIN_IN is your input 32 Mhz clock
CLKFX_OUT is the new 25 Mhz clock
CLKIN_IBUFG_OUT is a buffered version of your 32 Mhz clock
CLK0_OUT is your input clock at 0 phase (basically your input clock again).

Best Answer

Related Solutions

Electronic – Reset signal for fpga evaluation board

Using Digital Clock Manager with Verilog to generate 25Mhz clock from 32Mhz internal clock

Related Topic