Electrical – Logic Gate using Transistor and Diode not working on Proteus

And we know, that when we connect both diodes to GND (logic 0) , the current flows from Vcc to the two diodes as both are forward biased , and there will be no current passing through the output terminal because all of the current is flown through the diodes for the greater potential difference.

You are already confused. Specifically, "there will be no current passing through the output" is not necessarily true. For this kind of logic gate, and indeed most kinds of logic gates, we define the truth values by voltages, not by currents. For example, what about this?

^{simulate this circuit – Schematic created using CircuitLab}

Here, we have your AND gate. Both inputs are connected to ground (low, false). The output is false, which means a low voltage. But we've connected the output to a pullup resistor (R2), and there's current flowing through the output, via the path indicated by the arrows.

Think about why the output is a low voltage. With the diodes connected to ground, current can flow through R1 or R2. What happens to a resistor has a current through it? There's a voltage across it, by Ohm's law:

$$ V = I R $$

How much current will flow? Exactly enough to make the voltage across the resistor equal to V1, less the voltage drop of the diodes.

In fact it doesn't matter what you connect to the output: current will flow until that output is at a low voltage (ground plus the voltage drop of the diode). If that's not true, then current will flow until it is, or you blow a fuse. Hopefully you are designing to not blow a fuse.

If however, neither of the diodes are connected to ground, then there's no path from the output to ground. Current will instead flow through R1. For the logic gate to work correctly, this needs to make the output voltage high, but here's where we run into a limitation of this kind of logic. Consider:

^{simulate this circuit}

With the inputs high, the diodes aren't pulling the output to near 0V. Instead, there's a path for current shown by the arrows. But what's the output voltage? R1 and R2 form a voltage divider. The current through R1 and R2 is equal, and they are of equal resistance, also. Thus we can infer from Ohm's law that the voltage across them is equal, and since they are connected across V1, the total voltage drop across them must be 5V. So, the output voltage is 2.5V.

That's not exactly what you want in a logic gate. Ideally, the output is 5V no matter what you put on the output. For this logic gate, that's only true if we leave the output open, or replace R2 with a much bigger resistor. This is a pretty limiting constraint, which is why this isn't a popular topology for a logic gate.

here comes my question. When both of the input diodes are connected to GND, there is a flow of current through the two diodes but why not through the LED?

Here's a simpler case to illustrate that problem:

^{simulate this circuit}

If it's not clear from that, try building it with just an LED, then just an ordinary silicon diode like 1N4148. What's the voltage across the diodes in these cases? Why is that?

^{simulate this circuit – Schematic created using CircuitLab}

Figure 1. The NAND gate is much simpler.

As you are discovering the AND gate is not so simple.

Try simulating this NAND gate and see how you get on. To make an AND gate you need to invert the NAND output. Note that in a logic chip that this would increase the propagation delay.

Note also that the I've added individual base resistors to prevent short circuiting the bases together.

From comment:

This isn't really answering my question. I was wondering about the AND gate, and also, my question is why wouldn't the output always be high? isn't the output just connected directly to +5v through R1?

No. The output in my Figure 1 is connected to a potential divider consisting of R1, Q1 and Q2. If both Q1 and Q2 turn on their resistance will be much lower than R1's and the output voltage will be pulled low - to about 2 x \$ V_{SAT} \$ = 2 x 0.2 = 0.4 V or so.

Your AND gate suffers a few problems. One major one is that using NPN transistors in that configuration you lose 0.7 V on the base-emitter junction. Anyway, as you have seen, the bias through the bottom transistor tends to raise the emitter voltage.

To have the resistance in the negative leg of your "AND" gate you would have to use PNP transistors.

^{simulate this circuit}

Truth table
In1  In2  OUT
0    0    1
1    0    1
0    1    1
1    1    0

This is still a NAND gate! You need an inverter after it to create an AND.