Electrical – Maximum SPI speed of TFT display

What your scope shows is a classic example of jitter, which means an error in the timing of an event (rising or falling edge), independent of whether there's any voltage noise on the signal.

But what can cause the jitter in your system?

• As you speculate, if the uC main clock is jittery that jitter will most likely transfer directly to the clock output from the SPI peripheral.

  Inadequate bypassing (you should have additional bulk bypassing on your board in addition to the two 100 nF capacitors you've drawn) could lead to jitter in the uC clock circuit.

  Power supply noise introduced by other circuits on your board could also have this effect (but would be reduced by more bypassing).

• The jitter could be inherent in the performance of the uC's SPI peripheral. It has to generate the SPI clock with reference to the system clock. If it uses a simple divider (4-to-1 in the case of 8 MHz system clock and 2 MHz SPI clock) you wouldn't expect to see much added jitter at all (though system clock jitter would pass right through). But if it uses a more complex scheme, like a PLL, that circuit could be varying the SPI clock pulse widths to keep in sync with the system clock, and you would see that as jitter. A PLL circuit could also be particularly sensitive to power supply noise.

If the jitter amplitude is limited to a small fraction of the clock period, as it seems to be here, there's no reason this jitter will cause errors on the SPI bus (in agreement with your observation that the SPI bus appears to work as expected).

A few points. That Maxim article targets a specific type of spi device. Mainly ones that are write only. Notice only MOSI is shown, not MISO. Additionally, these devices are chained, so data is shifted from one device to the other, like a shift register. (One common use of SPI peripherals on a microcontroller is to use them to drive common shift registers.)

SPI does not require the master to receive data. A slave is not required to respond. You can even have read only SPI devices, where the Master just clocks in data from the Slave (Only uses MISO). You can even have a 3 wire variation where MOSI and MISO are tied together (half duplex only). It all depends on the type of spi device you are using. Additionally, SPI can do Full Duplex transfers, but not all devices support this. As Wikipedia states, most devices do half duplex, even when wired in 4-wire mode.

In that note, the SPI devices are write only.

As for the clock frequency question, there is no auto negotiation of clock speeds. This is decided while the master is being programmed. You have to account for it.