Electrical – MOSFET Low Voltage Output

First off, great job so far. There are certainly chips and modules that could do this for you and at efficiencies higher than one could realistically obtain using discrete circuitry, but using them would be of little educational value. Just playing around and reinventing the wheel from stuff on hand is a great way to learn, and it looks like you're doing the 'playing around' part very well. And an oscilloscope is an oscilloscope. The only difference between a 'professional' one and an arduino sampling as hard as it can is what you can measure. If the thing you are measuring can be measured accurately enough with an 'arduinoscope', then there is no difference between it and a 'professional' oscilloscope. Just be sure you can trust your code and it's a perfectly adequate tool for what you're doing.

Now, to actually answer your question!

There is nothing wrong with your comparator circuit. In fact, it's behaving exactly as it should. Which unfortunately is not how you expected or intended it to behave (electrons just don't care about our intentions, they do what they want!).

This is a common problem I've seen when someone at home with digital electronics starts getting into analog circuitry and thinks about it as if it were digital. It isn't. Things aren't high or low, on or off. And any closed loop control circuit (closed loop meaning the output can effect the input - in this case, the comparator can effect the voltage it sees at its inverting input) is going to settle on a specific operating point, or just oscillate uselessly (because it is unstable due to taking too long to react - or too out of phase with it's feedback).

Comparators are not digital. They behave very non-linearly if they are open loop, and are the most 'digitally' in that usage case. Open loop means their output will not effect their input. This is, of course, not the case in your circuit. And here is the dirty secret: comparators are just high gain differential amplifiers. In other words, they're op amps with internal resistors arranged in a differential amplifier topology for the sake of convenience. They have very high gain, but it is not infinite. If you have a closed negative feedback loop, exactly like you do, it is going to to behave like an op amp. It is not a digital logic gate, it's an analog component that is designed to interface with digital circuitry, but you're not using it like that.

Also, a MOSFET is not digital either. They are not switches. They are transimpedance amplifiers. In fact, BJTs behave much more like switches than MOSFETs do. FETs can be modeled as a voltage controlled resistor, and a very linear one at 'intermediate' voltages. What you call intermediate is known as the linear region - and MOSFETs have a very wide such region. Much larger than other semiconductors. A FET is about the least-digital switching element you can find.

As the gate voltage gets higher, it loses its linear voltage to Rds behavior, but to get to the point where it is 'on', it must cross that linear region. Your comparator is not going to turn on the MOSFET sharply because it will rapidly close in on the intermediate voltage, just like the op amp it secretly is, and do whatever it needs to to keep the voltage at its inputs the same. It's oscillating near the ideal control point due to being configured to be a comparator, but it WANTS to turn the MOSFET partly on, it wants to make it a resistor, and it is doing a decent job despite being configured for a very different purpose. The true nature and op amp heart of a comparator reveals itself.

Why does it want the FET to be a resistor? Because that is what it needs to do. If the voltage goes above its noninverting terminal, it will turn on the FET until the voltage drops below the inverting terminal, and it will back off. If it could, it would settle on a specific voltage that keeps the FET only turned on enough to keep the voltage at its terminals equal. It can't do that, but it is trying and it is still doing a half-way respectable job of achieving that, even if it is oscillating around the voltage instead of settling on it. It will never turn the FET on quickly, or even all the way, as that would make the panel voltage drop too much. The ATtiny is unable to react fast enough, and so the voltage over and undershoots all over the place, but the comparator is fast and reacts continuously.

And it's working perfectly. It's tracking the power point you've set for the panel. You've given it a resistor it can control, so it is going vary the resistance of the MOSFET as needed to keep the panel voltage near the set point. What you've built is a somewhat awkward constant power dummy load. It's getting hot because the panel can't deliver the power drawn by the 100Ω resistor, so the MOSFET is being used to dynamically add extra series resistance until a power point is tracked. But it will only add just enough resistance to track that power point, and lower or raise it to constantly consume that amount of power. So it should get hot. Not because anything is wrong, however. The circuit is working, or trying to. If you used a proper op amp, it wouldn't oscillate, and instead keep it at whatever resistance is needed to consume a fixed wattage from the panel.

This is why MPPT is hard. You can't track a power point by turning the load on and off, you just get massive voltage swings up and down like you see with your ATTiny. You can't deliver all the power to the load without switching something on and off, because anything else means burning up the excess power. This is fundamentally the same reason linear regulators operate as they do. This is, really just a linear regulator. It's regulating a voltage. It doesn't matter that it is the voltage from a solar panel. It's still linear, and it is still trying to keep that voltage at a set point. And the only way it will do that is by burning power off as heat. Which is exactly what it is doing.

There is no software problem here. No amount of software can overcome this problem, unfortunately. If you want efficiency, you cannot use linear power point tracking. You will need to make it switch (which I know was your original intention), and you will need an energy storage device that will be alternatively charged and discharged by the switch. What I just described, and what you are envisioning (even if you didn't realize it) is a switching regulator. I recommend an inductor as your energy storage device. A PWM control chip would work in place of the comparator. A TL494 is a classic.

There is no way to do this with any amount of efficiency in the way you've set up, no matter software or anything else. A MPPT controller is usually an input-tracking buck-boost regulator for that reason, and one that charges a battery or super capacitor through an inductor. Building such a circuit is beyond the scope of this answer, but it is certainly worth giving 'TL494 MPPT' a quick google. Image search brings up a lot of examples. You could even try to do it using the attiny85 controlling the MOSFET, but you'll need to add an inductor, diode, capacitors, some other components. Unfortunately, the problem is physics, and it has not really shifted to software as it is, though it might seem like it. No matter what you do, you'll not get around burning that power without first adding the necessary components in a switching topology.

Anyway, building that would certainly be a terrific way to learn about electronics - and the scary parts like inductance and magnetics. It is also not for the feint of heart. Either way, good luck!

This is not the way this site is to used. Because you have not shown your effort or attempt in solving it, I'll only give you hints for solving it.

Problem 1: It's an NMOS device. You should be able to recognize the nodes: Source, Gate and Drain. Now, the first step is to identify which mode of operation the NMOS is in. Hint: The gate and drain branches are tied. Figure out gate-source voltage. Use the the appropriate the drain-current formula and you're good to go.

Problem 2: If you are able to solve the first one using the hints I've given you, you'll be able to find out these:

• The branches: Gate, drain and source
• The device type: NMOS/PMOS.

Once you have identified them, try to find out their modes of operation. Hint is: The bottom gate-source voltage has more magnitude than the threshold (-1V). Consider the voltage between the branches joining the two devices to be some value Vx. Find its operation region and hence use the required drain current formula. Then, do the same for the upper device. Equate the currents.

That's a lot. Work out now and update here. You can say where you're facing the problem and what you did to over come it. Share it and one of us will definitely help you out.

Edit: Proceeding to finding a solution:

Problem 1: Here, in the NMOS device, the output is taken at the source. The drain and gate voltage are tied to the same potential level; therefore, the device is always in saturation. So, using the drain current formula for saturation region:

Id = kn(Vgs - Vt)^2 ; where kn= kn'*(w/L) called the gain factor; a constant.

Id = kn(0.7-Vout)^2 ; Vgs = Vg - Vs

Because Id is unknown, the value of Vout can't be obtained. But, you can observe their relation from a plot of Id against Vout, wherein Vout = 0V when Id is at a maximum value, and it decreases non-linearly to Id=0 Amp giving Vout= 0.7V.

You are partially right in the sense that the Vout can't go above 0.7V because as soon as 0.7V value is reached, the device turns off. Rather than saying OFF and ON, it'd a good initial practice to mention the operating region; hence, cutoff region here. Below 0.7V, the device is conducting and is always in Saturation region (ON is traditionally used for device in triode/linear region).

To give more insights: (Read this only after you understood the remaining part). No conditions are mentioned for the given device, hence body effect and channel length modulations should be taken into consideration. For the latter, multiply a factor (1 + λVds), where λ is the channel length factor. There's a beautiful limitation you'll realize, if you take body effect into consideration; the threshold voltage of the device increases with the increase in Vout, and thus the Vout will be limited to a voltage lesser than 0.7V. From here we can conclude that NMOS can't pass a good high!

Problem 2: May be you are oblivious of the fact that PMOS/NMOS also have some resistance associated with them; hence a voltage drop is obvious. If you carefully observe, the currents in the two transistors is equal and, if you consider the MOS devices to be completely identical, then they form a series resistance network. If you apply voltage divider, equal voltage should drop between both of these; 0.5V between each device. Hence, the voltage at the node joining the devices(Vx, as I considered) is at 0.5V and Vout should be 0V, to give a 0.5V drop at the upper MOS device.

Both of these questions demand more qualitative understanding of the MOSFETs than just knowing the basic mathematics surrounding them. Hope I cleared a bit, will help you if you still have any confusion.