The root of the problem to be solved by this circuit is that the Drain of the upper FET is not at a fixed voltage level (goes up & down), and you have to supply about 10V relative to its Drain at the Gate to open it.
What exactly the bootstrap capacitor is doing over here ?
It creates a voltage that is about (almost) VCC + VS. Since VS is sometimes almost equal to the highest power supply line within the circuit (up to 500V or 600V, according to the drawing in the data sheet), there would be no way to get a voltage ~10V higher than that without some kind of "magic". The magic works by charging a capacitor through a diode to about Vcc when Vs is at GND (lower FET is conducting), and then this capacitor can provide the neccessary voltage level needed to open the Gate of the upper FET, and keep the Gate at a higher voltage even when the upper FET opens and VS goes up.
Here is an approach to quantitatively screen for a MOSFET most likely to match requirements. Equations used here will be based on those from the thread "micro, MOSFET, and DC motors", but will be rearranged and reformulated to better reflect MOSFET datasheet parameters.
Basic Static Criteria:
\$V_{\text{DS}}\$ ~ \$1.5 V_{\text{s-max}}\$ :
\$V_{\text{DS}}\$ shouldn't be less, but also shouldn't be much higher than 1.5 times supplied voltage.
\$V_{\text{Drv-min}}\$ > 2\$V_{\text{th-max}}\$:
If peak drive voltage is less, the FET channel conduction will not be fully enhanced.
\$\text{$\Delta $T}_{J-A}\$ < 50C : In the approach that will be shown, temperature rise and part thermal resistance will be used to set overall power criteria. The aim is to keep FET junction temperature less than 120C, which a temperature rise of 50C will do even if the ambient temperature is 70C. For a more reasonable ambient temperature of 50C a \$\text{$\Delta $T}_{J-A}\$ of 50C, of course, results in a junction temperature of 100C, which is what we'll use in the selection criteria.
Total power dissipated in the FET will be temperature rise divided by thermal resistance:
\$P_T\$ = \$\frac{\text{$\Delta $T}}{\Theta _{\text{JA}}}\$= \$P_{\text{cond}}\$ + \$P_{\text{sw}}\$ = \$R_{\text{ds}}\$ DC \$I_d^2\$ + \$ I_d V_s F_{\text{PWM}} \tau\$
where DC = duty cycle and FET switching time \$\tau\$ = \$\frac{2 R_g Q_{\text{mp}}}{V_{\text{drv}}}\$,
I will state, without proof, that the lowest power will be attained by having \$P_{\text{sw}}\$ = \$P_{\text{cond}}\$. Therefore in the following equations, both \$P_{\text{cond}}\$ and \$P_{\text{sw}}\$ will be replaced by \$\frac{\text{$\Delta $T}}{2 \Theta _{\text{JA}}}\$, or 1/2 \$P_T\$.
Dynamic Selection Criteria:
Then selection equations for \$R_{\text{ds}}\$ and \$Q_{\text{mp}}\$ can be written as:
\$R_{\text{ds}}\$ = \$\frac{ \text{$\Delta $T}}{3 I_d^2 \text{ DC } \Theta _{\text{JA}}}\$ : Recall that \$R_{\text{ds}}\$ here is scaled by 2/3 to account for junction temperature of 100C and positive temp coefficient of \$R_{\text{ds}}\$
\$Q_{\text{mp}}\$ = \$\frac{3 \text{$\Delta $T} V_{\text{drv}}}{4 I_d F_{\text{PWM}} R_g \Theta _{\text{JA}} V_s}\$
Example:
For this case the defining parameters are:
- \$V_s\$ = 170V
- \$F_{\text{PWM}}\$ = 150kHz
- \$I_d\$ = 3Amperes
- \$V_{\text{drv}}\$ = 10V
- \$\Theta _{\text{JA}} \$ = 62C/W (for TO-220 or TO-263)
- \$R_g\$ = 20 Ohms
- DC = 0.5
These yield search parameters:
- \$V_{\text{DS}}\$ = 250V
- \$V_{\text{th-max}}\$ < 5V
- \$R_{\text{ds}}\$ =\$\frac{\text{50C}}{\text{(3)(9)(0.5)(62C/W)}}\$ = 59.7mOhms
- \$Q_{\text{mp}}\$ = \$\frac{\text{3 (50C)(10V)}}{\text{4 (62C/W)(3A)(150kHz)(10Ohm)(170V)}}\$ = 1.28nCoul
Here is the search result from Digikey
The best match was an IPP600N25N3 , which had a \$Q_{\text{mp}}\$ of 3nCoul, so in order to meet power dissipation requirements either \$F_{\text{PWM}}\$ would have to be lowered to about 50kHz, or a heat sink would be needed to lower thermal resistance.
Best Answer
It's easier to understand with a drawing:
simulate this circuit – Schematic created using CircuitLab
The way you propose to use the NMOS as a high side switch is correct, you have to take the gate voltage above the supply voltage.
Let's use Vctrl = 10 V to open the NMOS and the supply is 50 V, that means there must be 60 V at the gate. Note that that is 60 V referenced to ground.
That -20 V / + 20 V limitation of the NMOS is for the NMOS itself, for its Vgs. That Vgs is the voltage across the Gate and Source of the NMOS. Since the source of the NMOS is at 50 V when the NMOS is switched on, the Vgs will be 10 V, not 60 V. So this condition is allowed and OK.
But watch out! If you now want to switch the NMOS off you might have a problem. Let's say you make Vctrl = 0 V then the gate will be at 50 V. That will not turn off the NMOS will as the voltage at the source will drop until it opens the so much that the NMOS will still conduct somewhat. It will work as a source follower. Avoid that ! What needs to be done is to make the Vgs of the NMOS itself equal to zero.
In order to do that you need to take the Gate all the way down to 0 Volt so ground. That means 0 Volt referenced to ground, just making Vgs = 0 is not enough as explained above. For this we would need to make Vctrl = -50 V !