Electrical – Non-Inverting Tri-State buffer with transistors only possible

A tristate buffer has a certain minimum time from when the enable is asserted to when its output impedance starts to fall (the drivers start to turn on). Also, it has a certain maximum time from when the enable is negated to when the drivers are fully off (high output impedance).

If the former is not greater than the latter, then you cannot use the same (well, inverted) enable signals directly for two buffers on the same bus; you need to guarantee the timing by other means — either by using different clock edges, or perhaps by using a delay line.

A good way to build gates with limited numbers of transistors is to use RTL (resistor-transistor logic) techniques. For example, here is a NAND gate, which can be converted into an AND gate with an inverter:

^{simulate this circuit – Schematic created using CircuitLab}

The fan-in and fan-out capabilities of this type of logic are not great, which is why it was abandoned once the development of ICs made the incremental cost of transistors essentially negligible. But it can be used to build moderately complex logic circuits if you don't care too much about the speed.