Electrical – Print std_logic_vector in hexadecimal (VHDL)

As David says, if you're using this unclocked style, it is CRITICAL that you get the sensitivity list correct. The immediate updates are from inputs that ARE in the sensitivity list; the mysterious delays are from inputs that aren't - therefore the process sleeps until something else wakes it up.

This Q&A and this webpage give the rationale behind how and why signal assignment occurs in delta cycles; understanding this is ABSOLUTELY KEY to understanding VHDL an all too often overlooked.

Alternatively if your simulator supports VHDL-2008, turn on that support and replace process(ALUctrl,A,B) with process(all) and let the tools build the correct sensitivity list for you.

Loops in HDL are a tricky thing to use in a synthesizable manner. I would recommend simply reading in the input bits as a binary number, compare with 9, if it is greater subtract 10.