flipflop
I am currently studying flip-flops.
I understand the purposes of flip-flops, and that they can be made by using NAND or NOR gates.
But what are the reasons for making them these two ways? Does either way work for storing bits? Or is this just for cost consideration?
If I understand your question right, a simple centre tapped rectifier like this should do:
L1 is the primary winding, L2 and L3 are the secondary windings. OUT1 and OUT2 are to your FFs (or whatever you are capturing with) Ignore the 1Meg R3, it's just there to keep SPICE happy.
You can use the correct windings ratio to adjust the levels as desired (may be useful if high voltages are involved), and add e.g. a couple of zeners to protect your inputs. There are also many other ways to do this, depending on exactly what you are trying to do.
Simulation of above circuit (light blue is input pulse waveform, blue is negative pulse output, green is positive pulse output) EDIT - to make it clearer I simulated with a pulse file rather than a square wave as shown in the schematic:
If I understand the question, take the "clk" to one input of an XOR and the phototransistor - suitably biased - to the other XOR input. When "in sync" the output will be zero most of the time, except for delay between the "clk" and the sensor. A low-pass, perhaps an RC, followed by a schmitt trigger will tell if the signals are "in-sync" most of the time or not. If the delay is a large fraction of the "clk" period, then other circuitry would be required.
Best Answer
Even though the comments and the answers are quite reasonable, i would like to add some information that i assumed you didn't know based on your question
[CMOS]
Why NAND and NOR gates are the building blocks?
Because all the CMOS circuits are complementary circuits you can`t build a CMOS AND gate, you will end up building a NAND followed by NOT gate to form this AND gate, this is because PMOS is used as pull-ups while NMOS is used as pull-downs. For more information you should look into This question. The figures below shows the CMOS implementation of the NOR,NOT and NAND gates
What is the difference between NAND and NOR versions?
They both do the same logic function, but sometimes one of them is better than the other. Let me give an example
below are the NAND and NOR implementation for this logic function
One of the differences here is that A input in the NOR implementation is connected to only two transistors [NOT gate], while in the NAND implementation is connected to 4 transistors [2x NAND gates] which means that in the NOR version the A input have HALF THE CAPACITIVE LOAD than the NAND version
So in this example both versions differ in the loading on A input you might start worrying about this capactive load if for example A is connected to many other circuits
The gist is: depending on many factors one can decide which version is suitable for a circuit but both do the same function