Electrical – Quartus Prime Qsys HPS(Hard Processor System) Error

fpgaintel-fpgaquartussystem-on-chip

I'm trying to generate a system including HPS(Hard Processor System) of the Cyclone V SoC in Quartus Prime Qsys. At the "Generate HDL" stage I got the following errors. I'm not expecting all the error codes to be analyzed but I put them here because someone might have ecnountered similar errrors and solved it.

I'm using Quartus Prime 17.0 standard edition on Windows 10. I've tried the Quartus Prime versions 13.1, 15.1 and 16.0 still same errors. I tried different configurations on Qsys(connecting HPS to different hardware units, configuring the HPS in a different way) still got the same errors. Tried to create project in different levels of folders, no help. I would be glad if anyone has any opinion about it.

P.S: I know this isn't the exact community of stackexchange to ask this question but the possibility of someone from this community to encounter similar errors is high. So I tried my chance.

Error: border: Error during execution of script generate_hps_sdram.tcl: add_parameter: string not allowed for EParameterType, must be in {[INTEGER, NATURAL, POSITIVE, BOOLEAN, STD_LOGIC, STD_LOGIC_VECTOR, STRING, STRING_LIST, INTEGER_LIST, LONG, FLOAT]}
Error: border: Error during execution of script generate_hps_sdram.tcl: add_parameter AC_ROM_MR0   : null
Error: border: Error during execution of script generate_hps_sdram.tcl: set_parameter_property: No parameter AC_ROM_MR0
Error: border: Error during execution of script generate_hps_sdram.tcl: Could not load altera_mem_if_hps_emif
Error: border: Execution of script generate_hps_sdram.tcl failed
Error: border: 2017.05.20.17:09:19 Error: add_parameter: string not allowed for EParameterType, must be in {[INTEGER, NATURAL, POSITIVE, BOOLEAN, STD_LOGIC, STD_LOGIC_VECTOR, STRING, STRING_LIST, INTEGER_LIST, LONG, FLOAT]}
Error: border: 2017.05.20.17:09:19 Error: add_parameter AC_ROM_MR0   : null
Error: border: 2017.05.20.17:09:19 Error: set_parameter_property: No parameter AC_ROM_MR0
Error: border: Error during execution of script generate_hps_sdram.tcl: Could not load altera_mem_if_hps_emif
Error: border: Execution of script generate_hps_sdram.tcl failed
Error: border: 2017.05.22.01:36:18 Info:
Error: border: ********************************************************************************************************************
Error: border: 
Error: border: Use qsys-generate for a simpler command-line interface for generating IP.
Error: border: 
Error: border: Run ip-generate with switch --remove-qsys-generate-warning to prevent this notice from appearing in subsequent runs.
Error: border: 
Error: border: ********************************************************************************************************************
Error: border: 2017.05.22.01:36:22 Error: add_parameter: string not allowed for EParameterType, must be in {[INTEGER, NATURAL, POSITIVE, BOOLEAN, STD_LOGIC, STD_LOGIC_VECTOR, STRING, STRING_LIST, INTEGER_LIST, LONG, FLOAT]}
Error: border: 2017.05.22.01:36:22 Error: add_parameter AC_ROM_MR0   : null
Error: border: 2017.05.22.01:36:22 Error: set_parameter_property: No parameter AC_ROM_MR0
Error: border: while executing
Error: border: "set_parameter_property AC_ROM_MR0 DERIVED true"
Error: border: (procedure "_create_derived_mode_register_parameters" line 11)
Error: border: invoked from within
Error: border: "_create_derived_mode_register_parameters"
Error: border: invoked from within
Error: border: "alt_mem_if::gui::common_ddr_mem_model::create_parameters"
Error: border: (file "common_hps_emif.tcl" line 42)
Error: border: (file line 42)
Error: border: invoked from within
Error: border: "source common_hps_emif.tcl"
Error: border: (file "C:/intelfpga/17.0/ip/altera/alt_mem_if/alt_mem_if_interfaces/alt_mem_if_hps_emif/altera_mem_if_hps_emif_hw.tcl" line 22)
Error: border: 2017.05.20.17:09:19 Error: Could not load altera_mem_if_hps_emif
Error: border: add_fileset_file: No such file C:/Users/user/AppData/Local/Temp/alt7307_6443717614927326703.dir/0002_border_gen/hps_sdram.v while executing "add_fileset_file [file join $dest_subdir $dest_filename] $file_type PATH [file join $src_fulldir $filename]" ("if" then script line 54) invoked from within...

Best Answer

I found out that problem is the default language of Windows 10. I changed it into English(United States) (Start Menu->Settings->Time & language) and the errors are gone.

Related Solutions

Electronic – Quartus Prime: Automatically program .sof file after compilation

It takes a little bit more to get it working than that. The following template should work:

set module [lindex $quartus(args) 0]
set revision [lindex $quartus(args) 2]

if {[string match "quartus_asm" $module]} {

    #Commands which are run after the Quartus Assembler
    post_message "Running TCL after Quartus Assembler"

    #Use Chain file to program sof.
    qexec "quartus_pgm ProgramSof.cdf"
}

Place the template in a TCL script file of whatever name you choose, e.g. PostModule.tcl, then in your projects .qsf file, and the following line:

set_global_assignment -name POST_MODULE_SCRIPT_FILE quartus_sh:PostModule.tcl

The line in the .qsf file will instruct Quartus to run the TCL script each time a module (e.g. fitter, assembler, timequest, etc.) finishes running.

In the script we get the current module that is being run, and can also get the corresponding project revision. Then we check whether the current module is the one that we want to run the script after - in this case Quartus Assembler (quartus_asm).

Any commands you put within that if statement are now executed every time that the Quartus Assembler finishes.

The simplest way to achieve the programming is to use a chain file. If you open the Quartus programmer and set up everything - programming hardware, sof filename, device list, and so on. Then save that file as something like "ProgramSof.cdf". The template above will then execute the Quartus programmer using that chain file which will use all the settings you have saved.

You can also change the command to do it entirely via command line switches rather than a chain file, however if you are going to do this you need to specify the programming cable name, the devices in the JTAG chain if there is more than one (e.g. many dev kits have MAX V supervisors in the chain with the main FPGA), and so forth. It is easier to simply save a chain file and then if you need to change any settings you can just edit that chain file.

Electronic – Avoid using DSPs in Quartus Prime

There are two ways to achieve what you desire. One is a project setting, so will affect the entire design, which may or may not be desirable. The other way is module specific using attributes.

Project Wide

Open the project settings, and navigate to the "Compiler Settings" tab on the left. Click the button for "Advanced Settings (Synthesis)" to open the advanced settings window.

Find the option for "DSP Block Balancing", and select "Logic Elements".

This will completely disable the automatic inferring of DSP blocks, instead forcing all inferred multipliers to be implemented in logic.

Module Specific

The module specific alternative is to use the Verilog multstyle attribute to inform Quartus that you want to use logic based multipliers. To do this, add the following line directly above the module definition:

(* multstyle = "logic" *)

For example, you might have:

(* multstyle = "logic" *) module someMultipler ( ...

This will tell Quartus to use logic for any multiplier in this module.

You can do the same to request DSP blocks as well, using (* multstyle = "dsp" *)