Electrical – R2R vs String vs Delta Sigma

That's easy to answer with a general answer and immensely hard to answer in full detail that people have been writing books and papers about it for decades.

I've had some personal experience of this about 10 years ago when I implemented what was meant to be a simple and cheap SD converter (other side of same coin) with a mix of hardware and software and discovered a whole new world of opportunities to get unexpected results in the midst of normal behaviour.
Conclusions:

1. SD ADC have some major attractions and can be very cost effective, BUT avoid self implemented SD ADC if possible. Here there be Dragons - as material below amply indicates.

2. Use extra long barge poles when dealing with Z8 processors.

Here's the easy general answer to your question:

VERY roughly limit cycle oscillations (or spurious outputs or whatever) are spurious products that appear in an SD system in the presence of a constant input signal that should ideally be converted 'perefctly'. The constant input may be a DC level of a sinusoid or a mix of sinusoids which have a periodic function which interacts 'in some way' [tm] with the SD system due (probably) to the sampling period of the SD system not matching the period of the input system OR the SD having several stable states which it can flip between at certain points in the cycle. (Thing eg model railway circuit with many subloops and points which are switched randomly at certain locations).

That answer can be summarised as"makes funny outputs unexpectedly as a result of its nin-mlinera nature" and may sound excessively naive and simplistic.
As a demonstration of how well it's naive simplicity is reflected in the deeper ponderings of experts see this excellent discussion on pages 97 - 127. This is in a 2006 book "Analog Circuit Design". This chapter is intended to be about utilising limit cycle behaviour to impove SD modulator performance but along the way they give a good look at the deeper mysteries.

Glimpse into deep mysteries:

This very useful slideshow fromBerkley EE247 lecture 24 does a nice job of providing a "demystified" explanation and purports to provide a solution. It says:

Limit Cycle Oscillation

• Issue particular to SD modulator type data converters:

  • In response to low level DC inputs quantization noise becomes periodic and some of the components could fall with in the passband of interest and thus limit the dynamic range.

  • More pronounced in 1st order SD modulators compared to higher order (e.g. 2nd order)

BUT !!! - the following suggests that causes or solutions may not be quite that straight forward.

Here's a sample of perhaps the best related content from page 100:

This paper
Borkowski, Maciej, Digital Δ-Σ Modulation. Variable modulus and tonal behaviour in a fixed-point digital environment

says

• This work addresses a well known problem of unwanted spurious tones in the modulator’s output spectrum. When a delta-sigma modulator works with a constant input, the output signal can be periodic, where short periods lead to strong deterministic tones. In this work we propose means for guaranteeing that the output period will never be shorter than a prescribed minimum value for all constant inputs. This allows a relationship to be formulated between the modulator’s bus width and the spurious-free range, thereby making it possible to trade output spectrum quality for hardware consumption.

• Solution:

  • Use dithering (inject noise-like signal at the input ): to randomize quantization noise

  • If circuit thermal noise is large enough acts as dither

  • Typically, in the design of SD modulator integrating C values chosen carefully so that inband thermal noise level exceeds quantization noise

You are way over-thinking this. Given the long thermal time-constant of the system, there's no need to worry about high-order modulators, or how the sample rate of the sensors relates to the sample rate of the output.

Yes, delta-sigma is a good way to control the heater power, but a basic first-order implementation will be more than enough for your purposes. One side comment: it would be friendier for your power company to switch based on whole cycles, rather than half-cycles.

Your control loop produces an updated power setting at a 0.959 Hz rate. Let's assume that this setting is an integer between 0 and 255, representing 0 to 100% power.

You want to update the triac gate at a 60 Hz rate. Let's assume you have an interrupt that's synchronized to the rising zero crossings of the power line.

Set up your interrupt handler so that it has an 8-bit accumulator. On each interrupt, add the power-setting value to that accumulator, and if there's a carry out from the addition, turn on the triac for that cycle.

It really is that simple. The overall average duty cycle of the heater will match the power setting exactly. If you really feel you need higher resolution, you can use 16-bit values for the power setting variable and the accumulator in the ISR.