Electrical – Reducing the number of pins needed to read a 12-key keypad where the buttons are grounded

first, the Read-Modify-Write issue (from http://www.voti.nl/DB038/DB038-1-1.pdf, p51):

PICs use a funny IO architecture where a reading of a pin always returns the current external level of the pin, which can be different from the last value written to a pin, even when the pin is set as output, for two reasons:

• PIC instructions execute in a 2-stage pipeline, and for IO pins the read part of the next instruction takes place before the writing of the previous instruction.

• The load on the pin can be too high for it to reach its 'desired' level. This can easily happen (for a short time) when the load is capacitive, but it can also happen with a static load that is well within the normal operating specifications.

All PIC instructions that modify some bits in a byte are read-modify-write instructions, so when for instance two consecutive BCF (bit clear) instructions are executed on the same IO port the second instruction can ruin the effect of the first because of the first of the two reasons. Actually a BCF instruction (and a lot of other instructions, like INCF) on a port can ruin any previous setting of that port because of the second reason! It should be noted that the first reason occurs far more often, and can be avoided by placing a NOP or another instruction between any two read-modify-write instructions on the same IO port. But to really avoid all problems it is advised to allocate a separate register, do manipulations on that register, and copy it to the port register after each change. This technique is called a “using a shadow register”.

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Next: RC delay. When you change an I/O pin connected to a non-trivial amount of wire always wait a reasonable amount of time before expecting the result. In the absense of another source of 'reasonable': find out what seems to work, then double the time.

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Last: debouncing. AFAIK 50 ms is a reasonable upper limit for the bounce time of a switch. When your sample interval is longer than this time (you use 100 ms), you have no bounce problem. The proof is left as an excercise to the reader :)

The example circuit is given as this:

The important factor here is the voltage which the \$\overline{MCLR}\$ pin sees, and when.

Under normal operation the voltage should be high enough to register as a logic HIGH. When you want to reset, or wake up, the voltage must be low enough to register as a logic LOW.

With SW1 open, the voltage at point \$A\$, assuming \$V_{CC} = 5V\$, would be (once the capacitor \$C\$ is charged up) 5V. That is regardless of the value of resistors. Maybe 47KΩ causes too little current to flow to charge the capacitor fast enough? Unlikely, but possible. Try reducing the value of the capacitor (or try temporarily removing it altogether - it's not a component that's critical to the operation of the chip, only the wakeup system).

When you close SW1 with RB2 low the resistors R1, R2 and R7 form a voltage divider. The voltage at point \$A\$ would be \$V_A=\frac{R2 + R7}{R1 + R2 + R7}×V_{CC} = \frac{4800}{51800}×5 = 0.463V\$.

That should be low enough to register as a logic low. In the datasheet a logic low for \$\overline{MCLR}\$ is defined as \$V_{IL} = 0.15×V_{CC}\$, so for a 5V supply it would be 0.75V.

However, reducing R1 to 4.7KΩ would massively change that voltage:

\$V_A=\frac{R2 + R7}{R1 + R2 + R7}×V_{CC} = \frac{4800}{9500}×5 = 2.526V\$

That's way too high to register as a logic LOW, so a reset will never happen.

So you need to ensure that the ration between R1 and R2+R7 (and of course R1 and R3+R8) is correct. If you reduce R1 you must also reduce R2 and R3 accordingly.

Maybe going to R1=10KΩ and R2 / R3 = 1KΩ might bring it back into line with the datasheet.