Electrical – Regulated Cascode current mirror

Referencing the diagram from the linked article:

The drain current of either transistor is mostly determined by the respective gate-source voltage.

For the lower transistor, the gate-source voltage is just the input voltage

$$v_{GS1} = v_{IN}$$

For the upper transistor thought, the gate-source voltage is

$$v_{GS2} = 0 - v_{D1}$$

where, in this example \$v_{D1} < 0 \$.

Now, the drain voltage of the lower transistor \$v_{D1}\$ will, essentially, be whatever it needs to be such that the upper transistor transistor current matches the lower transistor current.

For example, if the input voltage rises, the drain current of the lower transistor will increase which will act to reduce \$v_{D1}\$ (make \$v_{D1}\$ more negative) which increases \$v_{GS2}\$ thus increasing the drain current of the upper transistor.

Transistor Q4 is in a feedback loop as well.

Fixed input current: The gate voltage of Q4 is fixed and set by Q1 and Q3. The transistor Q2 has also a fixed Vgs and acts as a current source. Since the currents through Q3 and Q4 are the same, Q3 and Q4 have the same gate-source voltage. The source of Q4 is at the same potential as the source of Q3. The feedback mechanism that sets Vgs of Q4 is the same as for a changing input current.

Changing input current: Any change of the input current changes the gate voltage of Q4 which results in a change of its source voltage. The feedback results from the output resistance of Q2. If Q4 lets more current pass than Q2 can sink, the drain voltage of Q2 goes up and reduces the gate-source voltage of Q4, which in turn reduces the current of Q4.