Electrical – Rising-edge or Falling edge Counter

counter

When designing an arbitrary count sequence synchronous counter using kanuagh maps and either JK or D flip flops, does it matter whether the flip flops are rising-edge or falling-edge triggered?

Best Answer

It doesn't matter

Assume you are designing a 1-Bit up counter Count_Pos Such that each positive clock cycle it will add 1 to whatever stored in its count register.

And another identical counter Count_Neg that will add 1 to whatever stored in its count register each negative clock cycle

Both of these counters do have a combinatorial circuit part and a sequential circuit part; Such that at positive or negative edge the sequential part captures the combinatorial part output and stores it. When you are doing a Boolean minimization using K-map you are talking about minimizing the combinatorial part of the circuit that is doing the addition operation not the part that is storing the output of this operation.

For an example these are two synthesized 1-bit up counter i`ve used Yosys to synthesize them

module Count_Pos(RST,CLK,OUT);
  input RST,CLK;
  output reg OUT;

  always @ (posedge CLK) begin
    if(RST) OUT<=0;
    else OUT<=OUT+1;
  end
endmodule // COUNTER

The circuit after synthesis

enter image description here

And the other module is

module Count_Neg(RST,CLK,OUT);
  input RST,CLK;
  output reg OUT;

  always @ (negedge CLK) begin
    if(RST) OUT<=0;
    else OUT<=OUT+1;
  end
endmodule // COUNTER

enter image description here

You can see that the synthesis tool replaces the positive edge triggered D-Flip flop [_DFF_P_] with a negative edge triggered one [_DFF_N_] while keeping the same combinatorial circuit part [Which is a simple NOR gate]

So whenever designing a counter or any other state machine. You are using K-map to minimize the combinational part of the circuit.

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