Electrical – Simulating LPM_counter on Modelsim gives ‘z’ (high impedance) output

modelsimprogrammable-logicquartus-ii

I'm trying to implement a simple 9-bit frequency divider using the LPM_counter Module.
Hardware and Software being used:

ALtera Max V-CPLD
Quartus II 64 bit Web Edition 15.0
ModelSim Altera Starter Edition 10.3d

I wrote a program in Block schematic format (BDF) adn downloaded it into the cpld and it works fine, giving the desired output. However when I try to simulate it in ModelSim it gives 'z' (high impedance) on all outputs.

For the simulation I created a Verilog file from the BDF file using the 'Create HDL design file fron current file' option in Quartus. Then I wrote A testbench to simulate a clock input for the LPM_counter module.

I've tried a lot of different things that I've read from different forums such as trying to run it without a testbench by giving a Clock input directly in ModelSim, trying reg outputs instead of wires and vice versa, amongst other things.

I've been stuck on this for a while now and really need it to work because I'll be needing ModelSim to make programs for some upcoming projects. I'm doing this to get used to the whole process before I actually work on it.

Btw I made a frequency divider using JK flipflops and that worked fine on both, the cpld and ModelSim simulation. Its just this black box module that I'm having problems with.

Source File (Converted to Verilog from .bdf)

module ninebitlpm(  myclk,  q );


input wire  myclk;
output wire [8:7] q; // only using the two most significant bits
wire    [8:0] q_ALTERA_SYNTHESIZED;

lpm_counter b2v_inst(   .clock(myclk),  .q(q_ALTERA_SYNTHESIZED));

assign  q[8:7] = q_ALTERA_SYNTHESIZED[8:7];

endmodule

module lpm_counter(clock,q);

/*synthesis black_box */
input clock; output [8:0] q;

endmodule

Testbench

`timescale 1us/1ns

module test_lpm();

reg myclk;
wire [1:0]q;

ninebitlpm mycounter(myclk, q);

initial begin myclk = 1; forever #1 myclk = ~myclk; end

endmodule

Best Answer

module lpm_counter(clock,q); is an empty black box.

To get it to simulate, you will need to use the actual HDL rather than the black box. There are two options:

You can delete that module declaration and instruct Modelsim to compile the HDL file that was produced when you used MegaWizard.
Copy the contents from the HDL file from (1) into your source file to replace the black box.

Related Solutions

Electronic – ModelSim Altera: simulating the “lpm_add_sub” module

According to Altera's knowledge base, it's a bug in their simulation library, which incorrectly has the parameter names defined only in lower case (it should, apparently, be able to accept either).

http://www.altera.co.uk/support/kdb/solutions/rd04192000_5867.html

Searching directly for the error message didn't turn it up, because the text of the error message appears to have changed since they added the description of the problem to their knowledge base.

Fortunately, for synthesis the lower case names are accepted just as the upper case ones (as used in the documentation) are.

Electronic – How to reference subsets of logic[31:0] in SystemVerilog

Is there a more elegant way I can have a simple logic [31:0] variable that can be easily referred to by various subsets of its wires without going through all of this verbose rigamarole?

Is there a syntax I can use with Quartus II and ModelSim that allows me to avoid having yet another extra variable when sending the struct instruction_r (or i or j) to a module that expects a logic [31:0]?

The answer to both is yes. Simple data types such as logic [31:0] and struct packed {...} can be directly assigned; casting isn't necessary especially if they are the same width.

Since everything is the same size (32 bits), direct assignment is allowed (example1):

instruction_r instr_r;
instruction_i instr_i;
instruction_j instr_j;

floper #(32) instruction_reg_r(.en(c_irwrite), .d(readdata), .q(instr_r), .* );

always_comb begin
  instr_i = instr_r;
  instr_j = instr_r;
end

The curly brackets ({}) can even be used (example2):

logic [5:0] op;
logic [25:0] addr;
logic [4:0] rs, rt;
logic [15:0] imm;
logic [4:0] rd, shamt;
logic [5:0] funct;

floper #(32) instruction_reg_r(.en(c_irwrite), .d(readdata), .q({op,addr}), .* );

always_comb begin
  {rs,rt,rd,shamt,funct} = addr;
  imm = {rd,shamt,funct};
end

Another approach is to use type parameters. See IEEE Std 1800-2012 § 6.20.3 Type parameters. In this case change the definition of floper to:

module floper #(parameter WIDTH = 8, parameter type INSTR_TYPE = logic[WIDTH-1:0] )
               (input  logic             clk, reset, en,
                input  logic [WIDTH-1:0] d, 
                output INSTR_TYPE        q);
  // ...
endmodule

Then update the parameter value in the instantiations of floper. example3:

instruction_r instr_r;
instruction_i instr_i;
instruction_j instr_j;

floper #(32,instruction_r) instruction_reg_r(.en(c_irwrite), .d(readdata), .q(instr_r), .* );
floper #(32,instruction_i) instruction_reg_i(.en(c_irwrite), .d(readdata), .q(instr_i), .* );
floper #(32,instruction_j) instruction_reg_j(.en(c_irwrite), .d(readdata), .q(instr_j), .* );

Streaming operators ({<<{}} and {>>{}}) are needed when translating between packed/unpacked values, see IEEE Std 1800-2012 § 11.4.14 Streaming operators, Casting is required for assignments that do not have a 1-to-1 relationship. Casting can also be used for tuncating or padding which is useful for avoiding size mismatch warnings. IEEE Std 1800-2012 § 6.24 Casting a full description and examples.