biasbjt
In many texts it is mentioned that the emitter resistor stabilizes the bias circuit. For example particularly for the below example:
Which quantity is aimed to be stabilized initially? Vbe?
And how does adding Re archives this? Can you give an example scenario so we can see that how Re works?
The simplified equations only work when you observe some basic assumptions. The most important being that the transistor is operating in it's linear region.
Leave out the transitor for a moment. How much current would you get through Rc if it was connected directly between the 20V supply and ground?
Then add in Re. You should end up with 20/(80 + 6.8) = 230 mA. This will be the maximum current that can possibly flow through the transistor. Given that there will be a small voltage drop across the transistor and errors from the resistor tolerance, that is very close to the measured value of 222mA.
Depending on what you are trying to achieve you may need to reduce the collector resistor or reduce the targeted collector current.
That there is no output start-up spike with the preregulator in place will be because the soft-start of the LM5118 adds tens of milliseconds to the time allowed for the bias to come up and actively control the gate of Q1. That's a pretty reasonable way to have a more controlled start. But let's set that aside to look at some of the other things that can happen during start up.
Start-up power sequencing is always a big concern with any power supply. Things can get quite involved, making sure that proper bias is present at the right time. Here are some common causes of overshoot on start up, in rough order of prevalence:
Integrator wind up. A precharge occurs on the integrator capacitor at start, causing a hard start.
Uncontrolled start of \$V_{\text{Ref}}\$. A unit step start of \$V_{\text{Ref}}\$ can cause an overshoot of output voltage.
Local bias voltage coming up late, or unbalanced start. Unbalanced start of bias can happen when there is bipolar bias voltage. Either the positive or negative output can come up first, in which case the output can rail.
Lack of termination at startup. If the output is unloaded at start, the output can overshoot and stay at an excessive level for an extended period.
All of these causes should be checked. Integrator wind up and controlled start of \$V_{\text{Ref}}\$ always have to be managed, and will get further attention here. Local bias sequencing and balance can take many forms and is hard to say much about specifically, but now that the local bias schematic has been added to the question, it is somewhat doubtful that any imbalance or delay would be severe enough to cause overshoot. Lack of termination is usually not a significant factor in a linear supply, but could make any existing overshoot more severe.
Integrator Wind Up
Without an active loop, such as under start up conditions, an integrator capacitor will always become excessively charged. High gain and any offset voltage or input bias currents of the OpAmp will combine to make this so. Then when the loop becomes active, the error amplifier is railed and the supply output overshoots. All practical integrator circuits used in power supplies have some means added to constrain charge up of the integrator capacitor. Quite common is placing a diode in parallel with the capacitor.
Here, \$D_{\text{Lim}}\$ is configured such that if the output of the amplifier should normally be higher than \$V_{\text{Ref}}\$, the amplifier will behave as an integrator. But, for output voltages lower than \$V_{\text{Ref}}\$ no excess charge up of \$C_9\$ will occur and the amplifier will only have unity gain. So, the amplifier can not end up railed to the negative bias voltage. No or minimal overshoot. In the case that amplifier output should be lower than \$V_{\text{Ref}}\$ during normal loop operation, \$D_{\text{Lim}}\$ connection can be reversed to prevent railing to the positive bias supply rail.
Sometimes using a diode is not restrictive enough, especially if \$V_{\text{Ref}}\$ is adjustable over a wide range. In this case a normally closed single pole single throw (NC SPST) analog switch can be used in place of \$D_{\text{Lim}}\$ to make the error amplifier have unity or some proportional gain during start up. At the proper time the analog switch is opened and the error amplifier becomes an integrator again. No overshoot.
Uncontrolled Start of \$V_{\text{Ref}}\$
An abrupt step in \$V_{\text{Ref}}\$ can cause overshoot or ringing at the output. Although this happens a lot at start up, it's not strictly a start up problem. A control loop with inadequate phase margin, anything less than about 68 degrees, will overshoot or ring with a step of \$V_{\text{Ref}}\$. Best way to handle this in general is to design the loop to have adequate phase margin. Best practice at start up is to initiate start with \$V_{\text{Ref}}\$ at zero setting and then ramp to the desired setting over a period of milliseconds.
Note: Initially it appeared that overshoot cause could be delay of local bias. Here is a test to verify and a possible solution offered.
Since it is crucial with this power stage to have active pull-down on Q1-G to maintain control of Q1-S, a crude pre-bias could be applied to Q3-B. A 50kOhm resistor, here shown as \$R_{\text{ff}}\$, could be connected from Q3-B to Q1-D. When voltage appears at Q1-D, Q3 would be turned on actively pulling down Q1-G. To make this work, D6 and D7 would have to be turned around, anodes tied together and R8, and D7-C to IC1A-1, and D6-C to IC2A-1 to allow Q3-B to be pulled down during regulation. This might be the simplest thing to do.
When \$R_{\text{ff}}\$ is not present, ripple rejection of the stage, open loop with \$D_7\$ cathode pulled low, is zero dB.
With \$R_{\text{ff}}\$ in place ripple rejection improved to 20dB. 50kOhm was chosen on a wim, and no effort was made to find a better value.
Best Answer
Assume there is no emitter resistor.
Increase in VCC will lead to increase in collector current, also base current. This may have negative effect. For example, the temperature will now increase because of higher current.. As temperature increases, Vbe of a transistor reduces further..
As Base emitter voltage drops, base current would gain further triggering rise in collector current and this will make the circuit less stable.
Adding the emitter resistor counter acts by slightly opposing the rise in collector current. Whenever there is a rise in collector current, the voltage drop across the emitter resistor increases. This voltage drop now acts as a negative feedback. Higher the drop across the resistor value, lesser will be the collector current due to lesser base current.
As VCC increases, voltage drop across emitter resistor increases and similarly when VCC falls, the voltage across emitter resistor falls enabling higher collector current due to increase in base current.
Ideally I would use resistor divide bias at this base side..and keep base current only a fraction of current flowing through to bias resistors.