Electrical – SPI and ADC timing diagram

You are correct that T4 is the critical parameter. This defines the timing window that defines valid data, and reading after this time will not guarantee that.

T7 appears informative, in the sense that the next data bit will appear at this time plus any internal setup, transition and settling time. What it does tell me is that you may make no assumptions about what data is on the output in this window between the end of T4 and the end of T7. The output may have valid driven data, but it is unknown as to what that data will be.

T7 is interesting - if you look at the maximum clock frequency (20MHz), that yields a minimum cycle time of 50ns. If you add the time (max) that the data may be held for (T7) and the guaranteed minimum hold time (considering data held on bit n and hold on bit n+1), they add up to that minimum cycle time.

It is highly likely that the internal registers have a 10nsec setup time (certainly the Din timing requires it, see T9), so we have, from Sclk transition at bit n (out):

40nsec max to bit n+1 appearing internally.

10nsec internal setup time (data bit appears at clock transition).

10nsec hold (guaranteed).

So from a clock transition at bit n to guaranteed hold for bit n+1 = 60nsec (max).

I am not sure exactly which chip you are using, but STM32F4 family has maximum ADC sampling rate 2.4 MS/s or 7.2 MS/s if you use 3 of ADCs in triple mode.

You are also missing that between main clock and ADC is one more prescaler which limit clock on APB2 bus. Maximum clock on APB2 is 90 MHz which has to be divided with 2 for maximum ADC clock of 45 MHz.

To actually achieve this sampling rate you need to consider data speed (7.2 MS/s* 12bit=86 Mb/s), which is way too fast for serial communications available on chip. What you could do is use DMA to gather samples on chip memory and later send then slowly to PC.