I'm trying to design a simple SRAM board (using a cypress Cy7c1011cv33) to connect to my lattice machox3 starter kit's pin connectors. But I have some design questions, after reading their "SRAM Board Design Guidelines". The guideline says "PCB should be designed to inductances as low as possible", but how high can the inductance be? also is it advisable to connect two SRAMs' address and data pins together? I ask because then the vias will be longer, which goes back to my question about inductance. I made a simple board with one sram ic, but I calculated (by hand not with kicad) its inductance to be 51nH and have no idea if thats okay or not.
I plan on using the SRAM near its full speed (100MHz) and I'm using kicad to design the board (only because I can keep the track length constant without having to pay a small fortune). This is the first time I'm trying to design something that works this fast I usually stick to PICs MCUs and analog circuits so any help is appreciated.
Best Answer
It means you route everything (all of the fast signals like address and data lines) on the top layer and for the signals you want running at 100MHz you run them as short as possible. If your trying to connect an SRAM off board, your probably not going to be able to do that without impedance control of the lines, and connectors.
The pic below shows an FPGA with an SRAM with most of the traces routed on the top layer. If you don't do this, then when it doesn't work you have to go through each signal and measure the delay and make sure its within bounds of the datasheet. That doesn't sound like much fun, so I follow the guidelines and overdesign.