Electrical – Syntax error near variable and range in VHDL

errorfpgavhdlvivado

I learnt Java last year and started to learn VHDL and implementation on BASYS3 this year. I am just trying to display numbers on the seven segment starting from 0 and each time a push button is pushed the number will increase. I am familiar with the input and output declarations but I was not able to declare my integer variable as follows in VHDL vivado;

architecture Behavioral of top_module is
begin
shared variable total_foul : integer range 0 to 5;
total_foul := 0;

It keeps saying that there is a syntax error near variable and range which I couldn't find out. Also I tried to write the code for seven segment in case statements as follows;

 begin
        case total_foul is        
        when 1 => LED <= "1001111"; -- "1" 
        when 2 => LED <= "0010010"; -- "2" 
        when 3 => LED <= "0000110"; -- "3" 
        when 4 => LED <= "1001100"; -- "4" 
        when 5 => LED <= "0100100"; -- "5" 
        when others => LED <= "0000001"; -- "0"

But this also states that there is a syntax error near when.

The overall code for now is;

entity top_module is
    Port ( increase : in STD_LOGIC;
           decrease : in STD_LOGIC;
           foul : in STD_LOGIC;
           anode : out STD_LOGIC_VECTOR (3 downto 0);
           LED : out STD_LOGIC_VECTOR (6 downto 0));

end top_module;

architecture Behavioral of top_module is
begin
anode <= "1111";
shared variable total_foul : integer range 0 to 5;
total_foul := 0;
begin
if foul = '1'  then
    if increase = '1' and decrease = '0' then
        total_foul := total_foul + 1;
    elsif decrease = '1' and increase = '0' then
        total_foul := total_foul - 1;
    end if;
    begin
        case total_foul is        
        when 1 => LED <= "1001111"; -- "1" 
        when 2 => LED <= "0010010"; -- "2" 
        when 3 => LED <= "0000110"; -- "3" 
        when 4 => LED <= "1001100"; -- "4" 
        when 5 => LED <= "0100100"; -- "5" 
        when others => LED <= "0000001"; -- "0"    

end Behavioral;

Thanks for everyone in advance.

Best Answer

Stripping out the parts of your code that are not problematic, we have:

architecture Behavioral of top_module is
begin
  shared variable total_foul : integer range 0 to 5;
  begin
  if foul = '1'  then
  begin
    case total_foul is        
      when 1 => LED <= "1001111"; -- "1" 
      when 2 => LED <= "0010010"; -- "2" 
      when 3 => LED <= "0000110"; -- "3" 
      when 4 => LED <= "1001100"; -- "4" 
      when 5 => LED <= "0100100"; -- "5" 
      when others => LED <= "0000001"; -- "0" 

end Behavioral;

The first issue is your shared variable. These can only be declared in a declarative region, in this case, it looks like you wanted it in the architecture declarative region, which is before the first begin in the code above.

The next problem is your second begin statement. What was this supposed to do? It looks more like you wanted to start a process here.

There is a 3rd begin after the if foul = '1' line. Again, what is this meant to do? It does not match any valid code pattern, so I suggest you just get rid of it.

Your case statement starts off OK, but where is the matching end case;?

Going back to the if foul = '1' line, it has no matching end if;.

You need to go back and look at some examples of simple VHDL architectures, then carefully write code with these in mind. Per a comment, you should also avoid using a shared variable until you really understand why you are using this, and not a signal or variable.

Related Solutions

Electronic – Problem getting VHDL syntax correct

VHDL accepts the ISO 8859-1 character set, this is UTF-8.

Your VHDL analyzer is having problems with some of the characters as a result of you copying the text directly from a book.

Your comments aren't delineated by two dashes (e.g. --), your double quotation marks all need to be replaced with ".

After which the VHDL code analyzes.

There's no discernible reason why d3, d2, d1, and d0 can't be replaced with a bit_vector. There may uses with the present port interface in the book.

Formal ports are associated with actual signals in an association list. It's possible to associate individual elements of a vector with a base element.

Converting between non-closely related types can be done with conversion routines:

-- bcd_7seg.vhd
-- bcd-to-seven-segment decoder
entity bcd_7seg is
    port(
    d3, d2, d1, d0: in bit;
    a, b, c, d, e, f, g: out bit
    );
end entity;
architecture seven_segment of bcd_7seg is
    signal input : bit_vector (3 downto 0);
    signal output: bit_vector (6 downto 0);
begin
    input <= d3 & d2 & d1 & d0;
    with input select
        output <= "0000001" when "0000",
                  "1001111" when "0001",
                  "0010010" when "0010",
                  "0000110" when "0011",
                  "1001100" when "0100",
                  "0100100" when "0101",
                  "1100000" when "0110",
                  "0001111" when "0111",
                  "0000000" when "1000",
                  "0001100" when "1001",
                  "1111111" when others;
-- separate the output vector to make individual pin outputs.
    a <= output(6);
    b <= output(5);
    c <= output(4);
    d <= output(3);
    e <= output(2);
    f <= output(1);
    g <= output(0);
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity bcd_tb is
end entity;

architecture foo of bcd_tb is
    signal d:  std_logic_vector (3 downto 0) := "0100";
    signal output:    std_logic_vector (6 downto 0);
begin
DUT:
    entity work.bcd_7seg
        port map (
            d3 => to_bit(d(3)),
            d2 => to_bit(d(2)),
            d1 => to_bit(d(1)),
            d0 => to_bit(d(0)),
            to_stdulogic(a) => output(6),
            to_stdulogic(b) => output(5),
            to_stdulogic(c) => output(4),
            to_stdulogic(d) => output(3),
            to_stdulogic(e) => output(2),
            to_stdulogic(f) => output(1),
            to_stdulogic(g) => output(0)
        );
end architecture;

You can also associate individual elements of an array type port with the base element type or use conversion functions as are shown above for converting between type bit and the element type for std_logic_vector.

Electrical – ERROR:HDLCompiler:806 Syntax error near “port”

Forgive any wrong interpretations but your terminology (code, call) suggests you may see VHDL as a 'program'. It is instead a descriptor language for describing a digital electronic circuit. Recognising that distinction is paramount and you'll get confused if you don't see it clearly and unambiguously. Try to see VHDL as what it is at its heart: a glorified circuit diagram. Avoid mental comparisons with software and computer programs, which are very different.

Describing VHDL further for what you need is beyond this post. But your source file should instantiate ('connect up the wires of') your component outside of any process within your architecture.

Best Answer

Related Solutions

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Electrical – ERROR:HDLCompiler:806 Syntax error near “port”

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