Electrical – T-flip flop in Verilog

flipflopverilog

I want to build a T-flip flop in Verilog. So far I have written the following code, but I wish they could see if it is correct please. The machine I was using to make the code is in the image.

module flopJK(q,j,k,c);
 input j,k,c;
 output q;
 reg q;
 always @(posedge c)
 begin
  case ({j,k})
   {1'b0,1'b0}:begin q=q; end
   {1'b0,1'b1}:begin q=1'b0; end
   {1'b1, 1'b0}:begin q=1'b1; end
   {1'b1, 1'b1}:begin q=~q; end
  endcase
 end
endmodule

Best Answer

Your title and question ask about a T flip flop, but then you post code for a JKFF.

While a TFF can be built from a JKFF (by tying the inputs together), you can accomplish a TFF in much simpler code:

module tff_sync_reset (
    data, clk, reset, q
);
 input data, clk, reset; 
 output q;
 reg q;

 always @ ( posedge clk)
 if (~reset) begin
     q <= 1'b0;
 end else if (data) begin
     q <= !q;
 end

 endmodule
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