Electrical – Using a single transistor & capacitor (DRAM) vs a flip-flop(SRAM) to store a single bit of data

The easiest flip-flop to understand is the SR (Set-Reset) flip-flop:

Normally both inputs are high. When you pull the \$/S\$ input low, output \$Q\$ will go high regardless of the other input. Since the other NAND gate sees now a high level on both its inputs the \$/Q\$ output will be low. Now, even when \$/S\$ goes high again, the other input will be low, so the output \$Q\$ retains its state. That's the most easy way to make logic "remember" something.

Starting from the SR flip-flop you can make more complicated registered logic, where the D flip-flop is the most used.

This circuit is sometimes presented as an edge-triggered D -flipflop, but it's really level triggered, where \$CLK\$ is used to gate the \$D\$ input. If \$CLK\$ is low both inputs of the SR flip-flop are high, and it retains its output state. When \$CLK\$ goes high the \$D\$ input decides whether \$/S\$ or \$/R\$ goes low, and the output will set accordingly, thus remembering the state of \$D\$ when \$CLK\$ went high. The difference with a real edge-triggered D -flip-flop is that the output will change with the input as long as \$CLK\$ is high. To make it an edge-triggered flip-flop you'll have to include some feedback that makes the \$CLK\$ go low again immediately after going high. The D-type latch, as it's called, will remember the input state at the time the \$CLK\$ input goes low; i.e. the output will stop changing after the \$CLK\$ goes low again.

This is an edge-triggered D flip-flop:

If I had to make a decision, I would say it looks closest to a D-latch. The problem is that a SRAM cell is not really analogous to a particular type of static CMOS storage because of the way it operates.

There's a few differences that make SRAM quite different:

1. Transistor sizes determine if the cell will work at all. Most static CMOS logic will come to the right answer regardless of the relative transistor sizes, but the ratios of (M1,M3) to (M2,M4) to (M5,M6) need to be carefully selected to ensure that the cell is writable and readable.
2. There is no specific input or output terminal (no D, CLK, or Q pins).
3. A SRAM cell requires substantial support circuitry to function. The word-lines and bit-lines must be driven and read correctly in order for data to be reliably stored and retrieved.
4. A SRAM cell is designed to operate in an array. While nothing precludes most latches or flip-flops from being used in an array, it would be unreasonable to use a SRAM bit as a stand-alone single bit storage.

While there are similarities, SRAM and DRAM don't share a close relationship between any of the stand-alone single-bit storage cells.