Electrical – Verilog BitSet Circuit

circuit-designsystem-verilogverilog

A specific type of bit-level manipulation consists in setting or clearing one single bit in a multi-bit value, given its index and its new value. This operation can be implemented in hardware by a BitSet circuit with the following interface:

  • Input x is a 4-bit value representing the original value.
  • Output y is a 4-bit value representing the modified value, after the bit-set
    operation.
  • Input index is a 2-bit value, ranging from 0 to 3, indicating the index of the bit to modify.
  • Input value is a 1-bit value set to 0 or 1, indicating the value that bit index should take in output y. Every other bit in y should match the corresponding bit in x.

Here's the code I have which I took from examples in class:

module BitSet(input [3:0]x,
         input [1:0]index,
         input value,
         output [3:0]y);
   always@(x,index,value);
   begin
      if (index = 2'b00) 
        y[0] = value;
     if(index = 2'b01)
        y[1]=value;
     if(index = 2'b10)
        y[2]=value;
     if(index=2'b11)
        y[3]=value;
   end
 endmodule

and here's the testbench:

module BitSet_tb();
    reg [3:0]x;
    reg [1:0]index;
    reg value;
    wire [3:0]y;

    BitSet uut(
      .x(x),
      .index(index),
      .value(value),
      .y(y)
    );

    initial begin
        $monitor ("%d %b %b %b %b", $time, x, index, value, y);
           x=4'b0000;
           index=2'b00;
           value=1'b0;
       #10 x=4'b0001;
           index=2'b01;
           value=1'b0;
       #10 x=4'b1111;
           index=2'b10;
           value=1'b0;
       #10 x=4'b1111;
           index=2'b11;
           value=1'b0;
       #10 $finish;
     end
 endmodule

When compiling, I get the following errors:

bitset.v:10: syntax error
bitset.v:12: error: invalid module item.
bitset.v:13: syntax error
bitset.v:14: error: invalid module item.
bitset.v:15: syntax error
bitset.v:16: error: invalid module item.
bitset.v:17: syntax error
bitset.v:18: error: invalid module item.
bitset.v:19: syntax error

Best Answer

You can simplify your code greatly by not trying to shoe-horn everything into procedural blocks.

Think about how you would implement this with actual logic components. You'd have a decoder and 4 multiplexers.

You can represent that in Verilog with just 4 assignments along the lines of

assign y[0] = (index == 2'b00) ? value : x[0];

As for the errors in your code, I suspect they come from assigning to y in a procedural block when y was not declared as a reg.

Also, your code has a functionality error, because it doesn't implement the requirement "Every other bit in y should match the corresponding bit in x."

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