Electrical – verilog packed v unpacked array error

portverilog

I'm new to verilog.

I'm trying to implement a 2:1 multiplexer on a FPGA development board (DE1-SOC altera) using built in switches and LEDs.

The following are the assignments that I'm using for the multiplexer, these pins are connected from the FPGA to the switches and leds on the dev board:

I'm getting this error on output LEDR[0];

declaring module ports or function arguments with unpacked array types
requires SystemVerilog extensions

I've googled unpacked v packed arrays but I cannot understand what is the issue, I just want to set this pin as an output.

SW[0] - select
SW[1] - input 1
SW[2] - input 2
LEDR[0] - output

This is the verilog

module ligths (SW[0], SW[1], SW[2], LEDR[0]);

input SW[0], SW[1], SW[2];

output LEDR[0];

assign LEDR[0] = ((SW[2] & SW[0]) | (SW[1] & ~SW[0]));  

endmodule

Best Answer

While Alex's answer is correct about the solution, the reason for the error specifically is that you are trying to define a 2D (unpacked) array as an input port which is only supported by SystemVerilog.

Two examples. Unpacked:

input unpacked [5:0];

Packed:

input [5:0] packed;

The former example is an array of six 1-bit signals. The latter example is an array of one 6-bit signal. There is a very distinct difference.

The following should get rid of the unpacked/packed error:

input [0] SW, [1] SW, [2] SW;

However as you can see it is just ugly. Additionally depending on how smart the compiler is, you may end up with errors about redefinition of the signal SW instead.

Instead you would use Alex's approach of:

input [2:0] SW;
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