Electrical – Verilog: Shift Register with feedback loop

shift-registerverilogvlsi

I am trying to simulate a 3 stage shift register with feedback loop using D-flipflop and XOR gate.

main.v:

module main(
d0,d1,d2,
 clk ,
 reset ,
 q0,q1,q2);

input clk,reset;

inout d0,d1,d2,q0,q1,q2;

dff df1(.d(d0),.clk(clk),.reset(reset),.q(q0));

dff df2(.d(q0),.clk(clk),.reset(reset),.q(q1));

dff df3(.d(q1),.clk(clk),.reset(reset),.q(q2));
xor1 exor1(.a(q1), .b(q2), .c(d0));
endmodule

dff.v:

module dff(
d,
 clk,
 reset,
 q);

input d,clk,reset;
output q;

reg q;

always @ ( posedge clk)
 if (~reset) begin
   q <= d;
 end  else begin
   q <= 1'b0;
 end

endmodule

main_tb.v:

module main_tb;
reg clk,reset;
 //reg d0,d1,d2,q0,q1,q2;
 wire d0,d1,d2,q0,q1,q2;
 initial
 begin
    clk = 0;
    reset = 1;
    #15
    reset = 0;

 end



always begin
    #5 clk = !clk;
    end
    main U0(
 .d0(d0),
 .d1(d1),
 .d2(d2),
 .clk(clk),
 .reset(reset),
 .q0(q0),
 .q1(q1),
 .q2(q2)
 );

endmodule

Now ISim doesnt simulate this code. Where am i going wrong?

EDIT: edited the testbench code. ISim is stuck at 0ps.

Best Answer

You have a reset signal in your code, but you never actually assert it.

Without that, the simulator cannot put the FFs into a known state, so they just show "unknown" forever.

Assigning values to your q wires in the testbench is useless — that just conflicts with the values that the dffs are trying to produce.

Related Solutions

Electronic – Verilog asynchronous reads of regs – and design question

Your code simulates two multiplexers. These are actually asynchronous components. The fact that Verilog requires data1_temp and data2_temp to be declared as reg's is a quirk of Verilog syntax and your choice of coding style, and doesn't mean these signals would be the outputs of storage elements in a physical implementation.

If you want to capture these values in actual registers, you need to add those explicitly:

reg [7:0] data1, data2;
always @(posedge someclock) begin
    data1 <= data1_tmp;
    data2 <= data2_tmp;
end

But I would like to know what this mini register file would be made of in hardware. Particularly, the 4x8 bit array consisting of k0,k1,k2,k3.

You haven't shown how these variables are assigned, so it's not possible to say how they are implemented. As your code showed, just declaring them as reg doesn't guarantee they are implemented with actual storage elements. If you assign them inside a block that begins always @(posedge clk) then very likely they are flip-flops, but there are ways you could code them that would make them synthesize differently.

I thought when it came to registers and arrays like this, you need a clock to read out data, like RAM?

You need a clock to update a (physical) register. You can read it out at any time. For example:

wire [8:0] sum;
assign sum = k0 + k1;

is perfectly valid code. sum will change whenever any of its inputs changes. If k0 and k1 are the outputs of flip-flops, their values will only change when there is a clock edge.

For another example, you could equally well describe your multiplexers with code like this:

reg [7:0] k0, k1, k2, k3;
wire [7:0] data1_tmp;
reg [1:0] reg1;
// k<n> and reg1 are assigned elsewhere.
assign data1_tmp = (reg1 == 0) ? k0 :
                   (reg1 == 1) ? k1 :
                   (reg1 == 2) ? k2 : k3;

how do I read from this tag_array and do the comparison all within the same clock cycle?

Let me repeat a key point for emphasis: You need to use a clock to assign a new value to a register (an actual hardware register or group of flip-flops). It's output is available at any time.

RAMs are different and how you access the contents of a RAM will depend on details of the type of RAM you use.

I got confused because frankly I don't know enough about memory hardware and how that's possible.

Another key strategy: When you are learning digital logic, I recommend you learn about the physical hardware first, and then work out or study how to simulate it in HDL second. So first, learn what a physical flip-flop is, then learn the standard Verilog methods of describing a flip-flop. Especially if you are trying to write HDL for synthesis, trying to write good code before you learn the capabilities of the underlying hardware will lead you down a lot of dead-end paths.

Electronic – Feedback loop in Verilog

I don't see any code that resets K0, K1, and K2, until the load state is used.

This means that on start-up, these registers have X value.

Therefore the outputs of u_mult1, u_mult2, and u_mult3 have X value.

Therefore the outpus of u_adder1, u_adder2, and u_adder3 get X value.

Therefore on the next clock edge, sum_out_old gets X value. Probably at the same time, the K variables get loaded with their values from the module inputs. But it's too late. Since sum_out is calculated from sum_out_old, it then becomes X, and sum_out_old is trapped in the X state.

The easy way to solve this is to have K0, K1, and K2 reset to 0 when rst_n is asserted (low), but you should consider if this is correct for your situation.

Best Answer

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Electronic – Verilog asynchronous reads of regs – and design question

Electronic – Feedback loop in Verilog

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