Electrical – VHDL Compile Error saying “Type of VARIABLE is incompatible with

vhdl

I am pretty new to the world of VHDL programming.

In a simple code, I am trying to make a simple BCD adder.

I assigned/declared variable as following

Port ( dipSW : in  unsigned (7 downto 0); ......


signal n1 : unsigned(3 downto 0); 
signal n2 : unsigned(3 downto 0); 
signal sum : integer range 0 to 31;

Inside the Archetecutre(not in Process), I tried to compile following code

n1 <= 9 when num1 > 9 else num1; 
n2 <= 9 when num2 > 9 else num2; 
sum <= n1 + n2;

However, I get following error

Type of n1 is incompatible with type of 9.
Type of n2 is incompatible with type of 9
type of sum is incompatible with type of +

Can someone tell me what I am doing wrong?

Best Answer

Welcome to how very strongly typed VHDL is. Unlike Verilog, you can't just use numbers together and have it work. Specifically, the VHDL types UNSIGNED and INTEGER are not compatible with the operations you have specified. Check out this set of lecture slides on VHDL arithmetic and look up the operations provided by NUMERIC_STD.

A fix may be to only use the UNSIGNED type and wrap constants in calls to TO_UNSIGNED(constant, width), ensuring matching types.

Related Solutions

Electronic – std_logic_vector to unsigned conversion throwing incompatible error

Problem here is that abus(i) is of type std_logic and no vector. Inserting a '0' helps to create a vector that can be casted to unsigned:

sum := sum + unsigned( '0' & abus(i) );

Here's a helpful numeric_std cheat sheet: http://www.lothar-miller.de/s9y/categories/16-Numeric_Std

Electronic – VHDL logical operation on integer

A better way than using std_logic_vector and the non-standard std_logic_arith and std_logic_signed libraries is to use IEEE.numeric_std.all; and make the counter unsigned (or signed in other contexts where you need negative values).

signal hcount  : unsigned(7 downto 0);

And you can perform conversions to and from integer, and bitwise operations:

hcount <= to_unsigned(123,hcount'length);

signal somereg : std_logic_vector(7 downto 0);
...
somereg(to_integer(hcount(2 downto 0)) <= <a bit value>;

However in the given example, the bitwise operations turn out to be unnecessary: instead of masking bits to extract a 3-bit register address, you could use division and mod operations. Synthesis tools (mostly) aren't stupid : divide and mod by powers of 2 are optimised into the obvious field extractions and don't even generate "and" gates.

signal hcount    : natural range 0 to 235;
signal reg_addr  : natural range 0 to 7;

signal somereg : std_logic_vector(7 downto 0);
...
reg_addr <= hcount mod 8;
somereg(reg_addr) <= <a bit value>;

One benefit of this (apart from fewer ugly type conversions) is that you still profit from the integer subtype you declared for hcount : incrementing it to 236 will raise an overflow error in simulation, allowing you to catch and correct logic errors early.

Best Answer

Related Solutions

Electronic – std_logic_vector to unsigned conversion throwing incompatible error

Electronic – VHDL logical operation on integer

Related Topic