Electrical – VHDL Error 10481 : no primary unit

fpgaquartussimulinkvhdl

I'm designing a circuit using Simulink to VHDL generator to be burned into a FPGA.
Simulink model works fine on Simulink, however, when I try to compile the VHDL code using Quartus II I get the following error:

Error (10481): VHDL Use Clause error at dsc_escalado.vhd: design
library "mylib" does not contain primary unit "sen"

My top level code is dsc_escalado.vhd which uses library "mylib" generated by Simulink, which contains a file named sen.vhd where CORDIC algorithm is used to generate sine waves.

All files where generated by Simulink, I haven't modify any line of code. It works on Simulink, but wont compile on Quartus.

Update
I have included all files in the project, However I get the same error. Here is the log generated by Quartus:

Warning (20028): Parallel compilation is not licensed and has been disabled

Info (12021): Found 0 design units, including 0 entities, in source file sen.vhd

Info (12021): Found 0 design units, including 0 entities, in source file sen_120_not_ascii.vhd

Info (12021): Found 0 design units, including 0 entities, in source file sen_240_not_ascii.vhd

Info (12021): Found 2 design units, including 1 entities, in source file dsc_escalado.vhd

Info (12022): Found design unit 1: DSC_escalado-rtl

Info (12023): Found entity 1: DSC_escalado

Error (10481): VHDL Use Clause error at DSC_escalado.vhd(90): design library "mylib" does not contain primary unit "sen"

Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 1 warning

The VHDL code for sen.vhd retrieved from the comment link

Editor's Note: The source file comment line in question shows

— Source Path: DSC_escalado/sen

while in the original the last three characters consisting of a space (x"20), a SUB (x"1A") and a LF (x"0A")in the original file. There isn't a way of demonstrating the illegal character without resorting to another tool due to the originally being iso8859-1 character mapping and the StackExchange network using UTF-8.)

-- -------------------------------------------------------------
-- 
-- File Name: hdl_prj\hdlsrc\DPWMfinal\sen.vhd
-- Created: 2018-06-27 14:40:51
-- 
-- Generated by MATLAB 9.0 and HDL Coder 3.8
-- 
-- -------------------------------------------------------------


-- -------------------------------------------------------------
-- 
-- Module: sen
-- Source Path: DSC_escalado/sen 
-- Hierarchy Level: 1
-- 
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

LIBRARY WORK;
USE WORK.ALL;

ENTITY sen IS
  PORT( clk                               :   IN    std_logic;
        reset                             :   IN    std_logic;
        enb                               :   IN    std_logic;
        angle                             :   IN    std_logic_vector(31 DOWNTO 0);  -- sfix32_En28
        sin                               :   OUT   std_logic_vector(31 DOWNTO 0)  -- sfix32_En30
        );
END sen;

This is how Quartus II shows the illegal character.

Best Answer

There are VHDL tools that won't accept non-graphic character or non-format effector character values in comments.

The comment line:

-- Source Path: DSC_escalado/sen

has three trailing characters comprised of character values x"20, x"1A" and X"0a", respective space, sub and new line ASCII characters. Unfortunately x"1A" is neither a graphic character nor a format effector.

See IEEE Std 1075-1993 13.1 Character set

The only characters allowed in the text of a VHDL description are the graphic characters and format effectors. ...

That includes comments.

While in -2002 or later (-2008 shown):

15.2 Character set

The only characters allowed in the text of a VHDL description (except within comments—see 15.9, and within text treated specially due to the effect of tool directives—see 15.11) are the graphic characters and format effectors. ...

The presence of non-graphic characters or non-format effector characters in comments is non-compliant with VHDL standards prior to revision -2002.

You'd expect QuartusII would be -1993 compliant and you'd expect an error message(s) (the architecture requires the primary unit be previously analyzed) as well visible status indicating the entity is not analyzed.

After substituting " ^Z" for the portion of the comment consisting of x"20, x"1A" byte values your design unit analyzes with a -1993 compliant VHDL tool. (My editors shows the tail of the comment that way, the character can be deleted as well).

Consider providing your primary design unit in your question unchanged with the comment intact allowing the readers to duplicate the problem. External links aren't guaranteed to persist for the lifetime of the question.

Simulink is doing something that would be harmless (while not being particularly useful) in later revisions of the VHDL standard.

VHDL -1993 and later use the iso8859-1 character set where graphics characters and format effectors can be shown as 8 bit character values belonging to ranges:

#define is_graphic_char(x)      (((x <= 0x7e) && (x >= 0x20)) || \
                                 ((x >= 0xa0)) )

#define is_format_effector(x)   ((x <= 0x0d) && (x >= 0x09))

(These are from an include file providing character classifiers similar to ctype.h in a VHDL analyzer implementation).

The problem was originally discovered by using ghdl:

ghdl -a sen.vhd
sen.vhd:14:34:error: invalid character, even in a comment
ghdl:error: compilation error

This provides a :line:character: location.

Fixing the problem either requires an editor that will display the iso8859-1 character set sufficiently to show where the illegal character is found, using an editor that tracks the pointer to line and character position, or a hex editor. (We could also brute force and replace anything close at hand.)

The 0A character is a LF end of line which normally wouldn't be removed.

Related Solutions

Electronic – Why does this simple VHDL pattern for a shift register not work as expected

It has to do with what can be easily evaluated at elaboration time, formally, what is called a "locally static expression". This is an obscure looking rule, but it deserves some thought - eventually it does make some sense, and your simulator is quite correct in alerting you by generating non-obvious results.

Now, temp(1) can be evaluated at compile time (even earlier than elaboration time) and it can generate a driver on bit 1 of "temp".

However, temp(i) involves a bit more work for the tools. Given the trivial nature of the loop bounds here ( 1 to 4 ) it is obvious to us humans that temp(0) cannot be driven and what you are doing is safe. But imagine the bounds were functions lower(foo) to upper(bar) in a package declared somewhere else... now the most you can say with certainty is that temp is driven - so the "locally static" expression is temp.

And that means that the process is constrained by these rules to drive all of temp, at which point you have multiple drivers on temp(0) - the process driving (no initial value, i.e. 'u') and the external temp(0) <= '0';. So naturally the two drivers resolve to 'U'.

The alternative would be a "hacky little rule" (opinion) that if the loop bounds were constants, do one thing, but if they were declared as something else, do something else, and so on ... the more such oddball little rules there are, the more complex the language becomes... in my opinion, not a better solution.

Electronic – Problem getting VHDL syntax correct

VHDL accepts the ISO 8859-1 character set, this is UTF-8.

Your VHDL analyzer is having problems with some of the characters as a result of you copying the text directly from a book.

Your comments aren't delineated by two dashes (e.g. --), your double quotation marks all need to be replaced with ".

After which the VHDL code analyzes.

There's no discernible reason why d3, d2, d1, and d0 can't be replaced with a bit_vector. There may uses with the present port interface in the book.

Formal ports are associated with actual signals in an association list. It's possible to associate individual elements of a vector with a base element.

Converting between non-closely related types can be done with conversion routines:

-- bcd_7seg.vhd
-- bcd-to-seven-segment decoder
entity bcd_7seg is
    port(
    d3, d2, d1, d0: in bit;
    a, b, c, d, e, f, g: out bit
    );
end entity;
architecture seven_segment of bcd_7seg is
    signal input : bit_vector (3 downto 0);
    signal output: bit_vector (6 downto 0);
begin
    input <= d3 & d2 & d1 & d0;
    with input select
        output <= "0000001" when "0000",
                  "1001111" when "0001",
                  "0010010" when "0010",
                  "0000110" when "0011",
                  "1001100" when "0100",
                  "0100100" when "0101",
                  "1100000" when "0110",
                  "0001111" when "0111",
                  "0000000" when "1000",
                  "0001100" when "1001",
                  "1111111" when others;
-- separate the output vector to make individual pin outputs.
    a <= output(6);
    b <= output(5);
    c <= output(4);
    d <= output(3);
    e <= output(2);
    f <= output(1);
    g <= output(0);
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity bcd_tb is
end entity;

architecture foo of bcd_tb is
    signal d:  std_logic_vector (3 downto 0) := "0100";
    signal output:    std_logic_vector (6 downto 0);
begin
DUT:
    entity work.bcd_7seg
        port map (
            d3 => to_bit(d(3)),
            d2 => to_bit(d(2)),
            d1 => to_bit(d(1)),
            d0 => to_bit(d(0)),
            to_stdulogic(a) => output(6),
            to_stdulogic(b) => output(5),
            to_stdulogic(c) => output(4),
            to_stdulogic(d) => output(3),
            to_stdulogic(e) => output(2),
            to_stdulogic(f) => output(1),
            to_stdulogic(g) => output(0)
        );
end architecture;

You can also associate individual elements of an array type port with the base element type or use conversion functions as are shown above for converting between type bit and the element type for std_logic_vector.

Best Answer

Related Solutions

Electronic – Why does this simple VHDL pattern for a shift register not work as expected

Electronic – Problem getting VHDL syntax correct

Related Topic