Electrical – VHDL: What is correct way to model open collector output for FPGA

fpgai2ctestbenchvhdl

I2C uses open collector outputs. FPGAs do not have such outputs. They do have tri state buffers though.

  1. How should open collector output be defined in a VHDL for an FPGA?
  2. How should open collector output be pulled high in testbench? i.e how model the pull up resistor e.g on SDA line that connects master to slave, in a testbench?

Best Answer

FPGAs have tri-state outputs :

sda <= 'Z' when dout='1' else '0';

There are also sometimes optional internal pull-ups, but they are not meant to drive external circuits, so an I2C bus will need an actual pull-up resistor.

VHDL std-logic type has 'H' and 'L' values to simulate pull-up and pull-downs. You can write

sda <='H';

in the test-bench to simulate a pull-up.

std_logic is a "resolved" type, a signal can have several drivers, and a resolution function is used to determine the final state : 'Z' + 'H' = 'H' , '0' + 'H' = '0'

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