Vivado Export Hardware Issue – Unknown Bitstream Solution


We have a Zynq project in Vivado 2017.4. I can generate the bitstream, in proj/proj.runs/impl_1/mybitstream.bit.

Then I want to import that configuration to my petalinux project so I use File > Export > Export Hardware..., make sure the Include bitstream is checked and keep the the Export location: <local to project> (which ends up in proj/proj.sdk).

That gives me a proj/proj.sdk/proj.hdf file, but when I unzip it, file mybitstream.bit is not the one in proj.runs/impl_1! (it actually is one from a previous build).

I have to import hardware description then manually overwrite the old bitstream:

$ petalinux-config --get-hw-description=proj/proj.sdk
$ cp proj/proj.runs/impl_1/mybitstream.bit petalinux-proj/project-spec/hw-description/

Does anybody know where the Export hardware function gets the bitstream? Maybe there is a way to "clean" a Vivado project? (there is no such option in Vivado).
So far we only modified logic in the PL but I fear that, when we add some BRAM or change some addresses, the whole hardware description will be wrong…

Best Answer

I posted the same on Xilinx Forum and I think it could be an issue with Vivado not properly cleaning the .sysdef file in proj.runs/impl_1/.

After manually deleting it and re-generating the bitstream (which was fast because most of it was already compiled), the export gave me the proper .hdf.

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