I have a suspicion that your problem might have to do with the bootstrap circuit, as detailed in section 5.3 of the data sheet. Some evidence leads to this conclusion:
You are likeley using larger MOSFETs than in the original design (because your overall power is greater), thus you are dealing with a higher gate charge, resulting in a higher current that must be delivered by the integrated bootstrap circuit. It could be that the bootstrap circuit dissipates more power than it was designed for and fails, sometimes resulting in a bad output driver for the high side MOSFET, sometimes taking the MOSFET with it. Adding an external, fast and high-voltage bootstrap diode might help. Note that the calculation in Eq. 9 of sect. 5.3 uses the typical on-resistance of the integrated bootstrap circuit. It's a better idea to use the max. value from table 4 which is twice as high.
Once the circuit goes into overload, you say that the frequency drops. During these prolonged on-times, the voltage across the external bootstrap capacitor might become too low to keep the high side MOSFET saturated, causing it to have a higher on-resistance, excessive losses and thermal overstress. However, in this case, it would be the high-side MOSFET that fails first. Check the voltage across the bootstrap capacitor. A bigger capacitor might help, but this will likely put more stress on the integrated bootstrap driver or the external diode that might be necessary anyway.
Another possibility could be that you are exceeding the maximum slew rates for the high-side driver. This might cause it to do weird things.
Concerning the negative spikes, an external protective clamping diode at each driver's output might help (K=Vout,HS; A=GND,LS and K=Vout,HS; A=GND,HS). Something as simple as a 1N4148 might be enough.
I think the reason for the confusion is this isn't a true ZVS (Mazilli) driver, at least, not like one I've ever seen.
ZVS Driver
Typically a ZVS driver is like this, where a center-tapped transformer primary is used in conjunction with a capacitor as an LC oscillator. Clever connection of the nodes via mosfets means that the FETs drive the LC tank at its resonant frequency.
Note: you don't need to use a center tapped transformer, it is merely commonly done to step up the output at the secondary. There is no reliance on magnetic flux linkage and thus you could do this with discrete inductors. An additional aside: you'll often see a single inductor in series with the supply before current gets to the center tap. This is used as a choke to limit current spikes.
In your circuit you've attached, you only have an inductor on a single side of the oscillator circuit. It will still oscillate, but less effectively as only half the circuit is used over a full period.
With this in mind, we can now get to your questions...
How is oscillation initiated?
This is an interesting question and slightly amusing because typically when it comes to simulating oscillators like this, you have the opposite problem in being unable to get it to oscillate! In the circuit I've shown, it's perfectly symmetrical, and so oscillation only begins because of mismatch between real components. At the beginning of the simulation, both FETs should fight to turn on exactly the same. Normally you could solve this by making one resistor value a few ohms off or changing the VTH of one FET slightly differently (this is what you'll have in reality anyway), and hence one will "win" the initial race and start the oscillations. From there, the resonant LC tank will take over and whether they are perfectly matched or not, it resonates.
I'm not 100% sure without reading source code for Falstad but my guess is they impose some kind of initial conditions that the circuit is asymmetrical at startup and hence it works at all. Why yours fails to reset though, is beyond me.
However, I've modified the circuit to be as I explained I've typically seen these.
Note that:
- This modified circuit does not have the same issue, and upon reset it starts oscillating immediately again.
- The output voltage is much higher than your simulated version (188 vs 134V), because both halves of the output period are being used effectively instead of just half.
- If you slow down the simulation, you'll note that your circuit has significantly more overlap where both MOSFETs are on. This burns a lot of power and takes away from the primary advantage of Mazilli ZVS drivers (hence the name Zero-Voltage-Switching). It's what lets ZVS drivers control so much power at such great efficiencies, and you're not getting that performance, which will require much more heatsinking if you're trying to build this.
How does one size the inductor for balanced tuning?
You don't. The balancing of the circuit is by-design, simply by having a symmetrical circuit in the first place. This is fundamental to you having half the circuit missing. Yours will oscillate, but never evenly, because each half of the circuit is asymmetrical. It doesn't matter how you size your inductor with this topology.
In the traditional design, the inductance is used along with the capacitor to set the switching frequency, and this is the primary factor in choosing its value.
\$ f = \dfrac{1}{2 \pi \sqrt{LC}} \$
Hope that answers your questions and for more good reading, check out these links here and here.
Best Answer
From your waveforms, it seems that the current through M4 M8 pair (right lower MOSFETs) is not zero at the time they stop conducting. This current (and the energy related to it) excites some oscillations. It is not important where they happen; it is the non-zero current that causes problem.
You can use current transformers (ferrite rings with ~100 turns winding, the latest loaded to few Ohms resistor, the ring is placed over the high current wire) to see what currents do you have.
And my last question is: why do you expect ZVS conditions for this circuit? I did not simulate it, but it is not obvious it works in ZVS mode.