Electrical – Why aren’t latch based designs common these days

asiccmosintegrated-circuitrtlvlsi

Almost every ASIC out there if flip-flop based. In summary, DFF is two latches pushed closely together. While in a latch based design you can "separate" these two latches apart and squeeze logic in-between them. There are several advantages to a latch-based design:

  1. Time borrowing: can relax timing a lot
  2. Reduced area and power consumption: you get the same logic with half of the registers

Disadvantages:

  1. Two-phase clocks with dead-time are necessary
  2. Hard to wrap your head around the concept
  3. Tools don't support the concept easily
  4. Hard to prototype. Every FPGA out there has a DFF in their cell, not a latch
  5. Hard to do a scan-chain

Are these disadvantages so severe that the latch designs were abandoned? I mean, if we had proper EDA tools and FPGAs we could still do it, right? Or am I missing something really important here?

Best Answer

Your "advantages" don't hold water.

Modern synthesis tools can move logic around registers to optimize timing, so latches offer no advantage there.

How do you get "half the registers" by splitting them? Sounds like the same number of registers to me.

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