Electrical – Why E = (Vc + Vr) in a circuit with a capacitor and a resistor in series

As Madmanguruman says, the capacitor is in the wrong place.

The opamp is trying to keep the voltages on it's inverting input the same as the non-inverting input, which is 240mV in your example above. To do this with just Rsense present, it must keep 480mA flowing through Rsense as you say.
Now, with the cap in series, it will actually work to charge the capacitor as you have it. However, the catch is that it will not be at a constant current, and the cap will only charge to 240mV, since this it what the opamp needs to keep the balance.
The cap does not pass DC, so the current is initially 480mA, and drops exponentially down to 0 as the voltage rises (and the voltage across the resistor drops)

Another thing to understand here is that a simulation is only as real as you make it, and in some cases the ideal components cause problems. It's quite common for the simulator not to converge or produce odd results if there is no DC path available. Also with a transient simulation, you sometimes need initial conditions set to observe a process.
For example, if I simulate the above circuit in LTSpice with an ideal 1F capacitor, the simulation does not converge (never finishes) If I add a high value of parallel resistance (10MΩ, this is actually very conservative for such a large value, probably be much lower) to provide a DC path, and (very roughly) simulate real world imperfect capacitor leakage, the simulation works:

Simulation:

The 240mV is produced by the 24nA across the 10MΩ resistance (24e-9 * 10e6 = 0.24V) However, the cap starts the simulation at 240mV. Is this what will happen in real life? It's unlikely, so we need to simulate things as it will be when power is switched on, or at least with the cap starting with 0V across it. The reason this happens (in SPICE at least) is because there is an initial DC operating point simulation done before the transient simulation starts.

If we do the same simulation with an initial condition specified, we can see the "interesting" bit that happens prior to reaching a steady state:

So remember to be aware of the difference between ideal and real world components. If simulation results appear strange, then try adding some ESR/ESL (equivalent series resistance/inductance) and parallel resistances to simulations that correspond with the components you intend to use (datasheet will give values usually)
Also be aware of tolerances, for which monte carlo simulation is very useful.

Finally, here is the circuit with the cap placed in the right place, (although you may want high side current limiting in your final circuit):

Simulation of current through cap and voltage across it, notice the constant 480mA up until the cap is fully charged to 4.8V (initial condition used again to see the cap charging):

One last thing, make sure you do not use the LM741 in your final circuit, it's completely obsolete. Choose a decent general purpose rail to rail input/output opamp (rail to rail means it can swing all the way to each rail at the output and handle voltages up to each rail at the input, many opamps, including the 741, cannot do this - another departure from the convenient world of ideal components)

The resistor and capacitor voltages are out of phase. Their peak values don't happen at the same time. You can see this in the CircuitLab simulation:

Your equation for the reactance of the capacitor ignores the phase. To include it, you need to use complex numbers:

$$X_C = \frac 1 {j 2 \pi f C}$$

where \$j = \sqrt {-1}\$. For a 1 microfarad capacitor at 55 Hz, this gives:

$$X_C = \frac 1 {j 2 \pi (55\ \mathrm{Hz} \cdot 1\ \mathrm {\mu F})} = -j2.89\ \mathrm{k\Omega}$$

To find the voltage across the capacitor, use your complex reactance in the voltage divider equation:

$$V_C = V_{in} \frac {X_C} {X_C + R} = 10.5\angle 0^\circ\ \mathrm {V} \frac {-j2.89\ \mathrm{k\Omega}}{-j2.89\ \mathrm{k\Omega} + 10\ \mathrm{k\Omega}} = 2.92\angle 74^\circ\ \mathrm V$$

The resistor voltage is the difference between the input voltage and the capacitor voltage:

$$V_R = V_{in} - V_C = 10.5\angle 0^\circ\ \mathrm {V} - 2.92\angle 74^\circ\ \mathrm V = 10.09\angle 16^\circ\ \mathrm V$$

So the peak resistor voltage is about 10 volts, the peak capacitor voltage is about 2.9 volts, and the phase difference between the two voltages is exactly 90 degrees.

The reason for the phase difference is that the capacitor voltage is always 90 degrees out of phase with its current, while the resistor voltage is always in phase with its current. Since the two components share the same current, their voltages must be 90 degrees out of phase with each other.